kit

commit fb361a2c5e14ae76e5020dc11420bca9d19d4a83
parent faf2962b92abeaaa068ef34fca5b3a1c9dfe85e1
Author: Ryan Sepassi <rsepassi@gmail.com>
Date:   Tue, 16 Jun 2026 19:29:01 -0700

doc: record arm32 DEPTH=full corpus state (355/425, residual reds enumerated)

Diffstat:
M
doc/plan/ARM32.md
 | 
16
+++++++++++++---

1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/doc/plan/ARM32.md b/doc/plan/ARM32.md
@@ -34,10 +34,20 @@ Phase-2 inventory below is implemented and qemu-validated:
   test. The freestanding fix to kit ld's linker-script location counter (interior
   `sym = .` after a glob) landed alongside.
 
-Remaining follow-ons (intentional, documented): tail calls; the AEABI alias
-layer + coroutine asm in the kit-self-built rt (needs broader kit-as coverage);
+`make test-cross TARGET=freestanding-arm32 DEPTH=full` (toy X) runs 355/425
+green; the ~70 reds are left RED on purpose (not skipped), and break down as:
+tail calls (~14 cases — `arm_emit_call` panics on `CG_CALL_TAIL`), wide-type
+(i64) hint intrinsics (`@expect`/scalar-intrinsic preserve-type), the
+single-thread TLS limitation below (threadlocal mutate/multi), `@memmove`, full
+inline-asm, and a couple of arch-specific cases (e.g. the aa64 privileged hints
+cross-compiled onto arm).
+
+Remaining follow-ons (intentional, documented): **tail calls**; the **AEABI alias
+layer + coroutine asm** in the kit-self-built rt (needs broader kit-as coverage);
+`@memmove` + the full inline-asm assembler; **wide (i64) hint intrinsics**;
 hard-float (FPv4-SP); DSP/ARMv7E-M; ARMv6-M/Thumb-1; full `-mcpu`/`-mfpu`
-parsing; `.ARM.attributes`; a real multi-threaded TLS path; `-O0` code density.
+parsing; `.ARM.attributes`; a real **multi-threaded TLS** path; `-O0` code
+density.
 
 ## Status — 2026-06-16 — Phase 1 (walking skeleton) LANDED