commit f1f725af88ed3d7b2eba1997e8062c362de159f1
parent 06640e69e30580006566fbf6b008456df0857fbb
Author: Ryan Sepassi <rsepassi@gmail.com>
Date: Tue, 21 Apr 2026 05:28:05 -0700
Build: generate p1_<arch>.M1 on demand from p1_gen.py
The per-arch DEFINE tables are now true build artifacts — gitignored
and regenerated by a Makefile rule whenever p1_gen.py changes. Drops
the `gen`/`check-gen` phony targets in favor of dependency tracking,
so there's no way to end up with stale generated files.
Grouped target (&:) because p1_gen.py writes all three files in one
invocation; `make clean` also removes them alongside build/.
Diffstat:
| M | .gitignore | | | 3 | +++ |
| M | Makefile | | | 16 | +++++++--------- |
| D | p1_aarch64.M1 | | | 238 | ------------------------------------------------------------------------------- |
| D | p1_amd64.M1 | | | 238 | ------------------------------------------------------------------------------- |
| D | p1_riscv64.M1 | | | 238 | ------------------------------------------------------------------------------- |
5 files changed, 10 insertions(+), 723 deletions(-)
diff --git a/.gitignore b/.gitignore
@@ -1 +1,4 @@
build/
+p1_aarch64.M1
+p1_amd64.M1
+p1_riscv64.M1
diff --git a/Makefile b/Makefile
@@ -64,7 +64,7 @@ PODMAN := podman run --rm --platform $(PLATFORM) \
# --- Targets ---------------------------------------------------------------
-.PHONY: all toolchain run run-all clean gen check-gen
+.PHONY: all toolchain run run-all clean
all: $(OUT_DIR)/$(PROG)
@@ -117,13 +117,11 @@ run-all:
-$(MAKE) --no-print-directory PROG=$(PROG) ARCH=riscv64 run
clean:
- rm -rf build/
+ rm -rf build/ p1_aarch64.M1 p1_amd64.M1 p1_riscv64.M1
-# Regenerate the per-arch p1_<arch>.M1 defs from p1_gen.py.
-# Running `make gen` overwrites all three files in place; `make check-gen`
-# exits non-zero if any are stale (useful for CI). See p1_gen.py.
-gen:
+# Generate all three per-arch DEFINE tables from p1_gen.py in a single
+# shot. Grouped target (&:) because p1_gen.py writes all three files
+# unconditionally. These are build artifacts — gitignored; the build
+# regenerates them on any p1_gen.py edit so there's no staleness risk.
+p1_aarch64.M1 p1_amd64.M1 p1_riscv64.M1 &: p1_gen.py
python3 p1_gen.py
-
-check-gen:
- python3 p1_gen.py --check
diff --git a/p1_aarch64.M1 b/p1_aarch64.M1
@@ -1,238 +0,0 @@
-## p1_aarch64.M1 — GENERATED by p1_gen.py. Do not edit by hand.
-##
-## Shared op-table lives in p1_gen.py; each arch's encoders expand
-## (op, register-tuple, imm) rows into native bytes. See P1.md for the
-## ISA spec and register mapping.
-
-
-## ---- LI — load 4-byte zero-extended literal from inline data slot
-DEFINE P1_LI_R0 4000001802000014
-DEFINE P1_LI_R1 4100001802000014
-DEFINE P1_LI_R2 4200001802000014
-DEFINE P1_LI_R3 4300001802000014
-DEFINE P1_LI_R4 5A00001802000014
-DEFINE P1_LI_R5 5B00001802000014
-DEFINE P1_LI_R6 5300001802000014
-DEFINE P1_LI_R7 5400001802000014
-DEFINE P1_LI_BR 5100001802000014
-
-## ---- SYSCALL / SYSOPEN — uniform (clobbers r0 only) across arches
-DEFINE P1_SYSCALL E80300AAF50301AAF60302AAF70303AAE00315AAE10316AAE20317AAE3031AAAE4031BAAE50313AA010000D4E10315AAE20316AAE30317AA
-DEFINE P1_SYSOPEN 600C8092080780D2010000D4
-
-## ---- Linux syscall numbers (per-arch table). LE-32 immediate operands for LI.
-DEFINE SYS_WRITE 40000000
-DEFINE SYS_EXIT 5D000000
-DEFINE SYS_READ 3F000000
-DEFINE SYS_CLOSE 39000000
-
-## ---- Reg-reg-reg arithmetic (tranche 1) --------------------------
-DEFINE P1_ADD_R1_R1_R2 2100028B
-DEFINE P1_ADD_R1_R1_R4 21001A8B
-DEFINE P1_ADD_R2_R2_R6 4200138B
-DEFINE P1_ADD_R2_R3_R1 6200018B
-DEFINE P1_SUB_R1_R1_R2 210002CB
-DEFINE P1_SUB_R2_R2_R6 420013CB
-DEFINE P1_AND_R1_R1_R5 21001B8A
-DEFINE P1_OR_R1_R1_R2 210002AA
-DEFINE P1_XOR_R1_R1_R2 210002CA
-DEFINE P1_MUL_R1_R1_R2 217C029B
-DEFINE P1_DIV_R1_R1_R2 210CC29A
-DEFINE P1_REM_R1_R1_R5 300CDB9A01861B9B
-DEFINE P1_SHL_R1_R1_R2 2120C29A
-DEFINE P1_SHR_R1_R1_R2 2124C29A
-DEFINE P1_SAR_R4_R4_R2 5A2BC29A
-
-## ---- Immediate arithmetic (tranche 2) ----------------------------
-DEFINE P1_ADDI_R1_R1_3 210C0091
-DEFINE P1_ADDI_R1_R1_1 21040091
-DEFINE P1_ADDI_R1_R1_NEG3 210C00D1
-DEFINE P1_ADDI_R4_R4_NEG1 5A0700D1
-DEFINE P1_ADDI_R1_R1_NEG2 210800D1
-DEFINE P1_ADDI_R0_R0_1 00040091
-DEFINE P1_SHLI_R1_R1_1 21F87FD3
-DEFINE P1_SHRI_R1_R1_1 21FC41D3
-DEFINE P1_SARI_R4_R4_1 5AFF4193
-DEFINE P1_ANDI_R1_R1_6 21047F92
-DEFINE P1_ANDI_R1_R1_7 21084092
-DEFINE P1_ORI_R1_R1_1 210040B2
-DEFINE P1_ORI_R0_R0_2 00007FB2
-DEFINE P1_ORI_R0_R0_7 000840B2
-
-## ---- LA + memory ops (tranche 3) ---------------------------------
-DEFINE P1_LA_R4 5A00001802000014
-DEFINE P1_ST_R1_R4_0 410300F9
-DEFINE P1_LD_R1_R4_0 410340F9
-DEFINE P1_ST_R1_R4_8 410700F9
-DEFINE P1_LD_R1_R4_8 410740F9
-DEFINE P1_SB_R1_R4_16 41430039
-DEFINE P1_LB_R1_R4_16 41434039
-DEFINE P1_ST_R1_R4_NEG8 41831FF8
-DEFINE P1_LD_R1_R4_NEG8 41835FF8
-
-## ---- Branches (tranche 4, LI_BR-indirect) ------------------------
-DEFINE P1_B 20021FD6
-DEFINE P1_BEQ_R2_R3 5F0003EB4100005420021FD6
-DEFINE P1_BNE_R2_R3 5F0003EB4000005420021FD6
-DEFINE P1_BLT_R2_R3 5F0003EB4A00005420021FD6
-DEFINE P1_BLT_R4_R2 5F0302EB4A00005420021FD6
-
-## ---- Control: CALL/RET + single-slot and N-slot PROLOGUE/EPILOGUE/TAIL
-DEFINE P1_PROLOGUE FF4300D1FE0300F9
-DEFINE P1_EPILOGUE FE0340F9FF430091
-DEFINE P1_RET C0035FD6
-DEFINE P1_CALL 20023FD6
-DEFINE P1_TAIL FE0340F9FF43009120021FD6
-DEFINE P1_PROLOGUE_N2 FF8300D1FE0300F9
-DEFINE P1_EPILOGUE_N2 FE0340F9FF830091
-DEFINE P1_TAIL_N2 FE0340F9FF83009120021FD6
-DEFINE P1_PROLOGUE_N3 FF8300D1FE0300F9
-DEFINE P1_EPILOGUE_N3 FE0340F9FF830091
-DEFINE P1_TAIL_N3 FE0340F9FF83009120021FD6
-DEFINE P1_PROLOGUE_N4 FFC300D1FE0300F9
-DEFINE P1_EPILOGUE_N4 FE0340F9FFC30091
-DEFINE P1_TAIL_N4 FE0340F9FFC3009120021FD6
-
-## ---- Seed-Lisp step 1 extensions (tranche 6) ---------------------
-DEFINE P1_MOV_R1_R6 E10313AA
-DEFINE P1_MOV_R6_R1 F30301AA
-DEFINE P1_MOV_R6_R0 F30300AA
-DEFINE P1_MOV_R0_R3 E00303AA
-DEFINE P1_MOV_R7_R0 F40300AA
-DEFINE P1_MOV_R7_R2 F40302AA
-DEFINE P1_MOV_R2_R6 E20313AA
-DEFINE P1_MOV_R3_R7 E30314AA
-DEFINE P1_MOV_R2_R7 E20314AA
-DEFINE P1_MOV_R4_R7 FA0314AA
-DEFINE P1_MOV_R2_SP E2030091
-DEFINE P1_MOV_R3_SP E3030091
-DEFINE P1_MOV_R4_SP FA030091
-DEFINE P1_MOV_R6_SP F3030091
-DEFINE P1_MOV_R2_R0 E20300AA
-DEFINE P1_LD_R0_R6_0 600240F9
-DEFINE P1_LD_R1_R6_16 610A40F9
-DEFINE P1_LD_R3_R4_0 430340F9
-DEFINE P1_LD_R0_R5_0 600340F9
-DEFINE P1_LB_R1_R4_0 41034039
-DEFINE P1_ST_R2_R4_0 420300F9
-DEFINE P1_ST_R0_R4_8 400700F9
-DEFINE P1_LD_R0_R4_8 400740F9
-DEFINE P1_LB_R1_R0_0 01004039
-DEFINE P1_LD_R0_R1_0 200040F9
-DEFINE P1_LD_R0_R1_8 200440F9
-DEFINE P1_ST_R1_R0_0 010000F9
-DEFINE P1_LD_R2_R4_0 420340F9
-DEFINE P1_ST_R2_R0_8 020400F9
-DEFINE P1_LD_R0_R4_0 400340F9
-DEFINE P1_ST_R2_R4_16 420B00F9
-DEFINE P1_LD_R2_R4_16 420B40F9
-DEFINE P1_LD_R0_R3_0 600040F9
-DEFINE P1_ST_R2_R3_0 620000F9
-DEFINE P1_ST_R1_R3_8 610400F9
-DEFINE P1_LD_R1_R3_8 610440F9
-DEFINE P1_ST_R2_R3_16 620800F9
-DEFINE P1_LD_R2_R3_16 620840F9
-DEFINE P1_LD_R1_R1_0 210040F9
-DEFINE P1_ADD_R2_R0_R1 0200018B
-DEFINE P1_BLT_R0_R2 1F0002EB4A00005420021FD6
-DEFINE P1_BLT_R1_R2 3F0002EB4A00005420021FD6
-DEFINE P1_BNE_R1_R2 3F0002EB4000005420021FD6
-DEFINE P1_BNE_R0_R2 1F0002EB4000005420021FD6
-
-## ---- Seed-Lisp step 3 extensions (tranche 9): strings + interning
-DEFINE P1_MOV_R0_SP E0030091
-DEFINE P1_MOV_R1_R3 E10303AA
-DEFINE P1_ADDI_R1_R7_7 811E0091
-DEFINE P1_ADDI_R1_R1_8 21200091
-DEFINE P1_ADDI_R1_R1_NEG5 211400D1
-DEFINE P1_ADDI_R2_R2_1 42040091
-DEFINE P1_ADDI_R2_R2_NEG1 420400D1
-DEFINE P1_ADDI_R3_R0_8 03200091
-DEFINE P1_ADDI_R3_R3_1 63040091
-DEFINE P1_ADDI_R3_R3_NEG1 630400D1
-DEFINE P1_ADDI_R6_R6_1 73060091
-DEFINE P1_ADDI_R7_R7_NEG1 940600D1
-DEFINE P1_SHLI_R0_R0_3 00F07DD3
-DEFINE P1_SHLI_R0_R0_52 002C4CD3
-DEFINE P1_SHLI_R1_R1_3 21F07DD3
-DEFINE P1_SHLI_R3_R0_5 03E87BD3
-DEFINE P1_SHLI_R6_R6_32 737E60D3
-DEFINE P1_SHRI_R0_R0_52 00FC74D3
-DEFINE P1_SHRI_R1_R1_3 21FC43D3
-DEFINE P1_SHRI_R6_R6_32 73FE60D3
-DEFINE P1_ORI_R0_R0_4 00007EB2
-DEFINE P1_ORI_R0_R0_1 000040B2
-DEFINE P1_ADD_R0_R0_R3 0000038B
-DEFINE P1_ADD_R2_R2_R0 4200008B
-DEFINE P1_ADD_R2_R2_R1 4200018B
-DEFINE P1_SUB_R3_R3_R0 630000CB
-DEFINE P1_BEQ_R0_R6 1F0013EB4100005420021FD6
-DEFINE P1_BEQ_R2_R6 5F0013EB4100005420021FD6
-DEFINE P1_BEQ_R3_R1 7F0001EB4100005420021FD6
-DEFINE P1_BEQ_R3_R6 7F0013EB4100005420021FD6
-DEFINE P1_BEQ_R7_R1 9F0201EB4100005420021FD6
-DEFINE P1_BNE_R0_R1 1F0001EB4000005420021FD6
-DEFINE P1_BNE_R0_R6 1F0013EB4000005420021FD6
-DEFINE P1_BNE_R0_R7 1F0014EB4000005420021FD6
-DEFINE P1_BNE_R6_R3 7F0203EB4000005420021FD6
-DEFINE P1_LB_R0_R1_0 20004039
-DEFINE P1_LB_R2_R6_0 62024039
-DEFINE P1_LB_R7_R2_0 54004039
-DEFINE P1_LD_R0_R2_0 400040F9
-DEFINE P1_LD_R0_R3_24 600C40F9
-DEFINE P1_LD_R1_R3_24 610C40F9
-DEFINE P1_LD_R3_R2_0 430040F9
-DEFINE P1_LD_R6_R1_0 330040F9
-DEFINE P1_LD_R6_R3_8 730440F9
-DEFINE P1_LD_R7_R3_16 740840F9
-DEFINE P1_SB_R1_R0_7 011C0039
-DEFINE P1_SB_R2_R3_0 62000039
-DEFINE P1_ST_R0_R2_0 400000F9
-DEFINE P1_ST_R0_R3_24 600C00F9
-DEFINE P1_ST_R0_R4_0 400300F9
-DEFINE P1_ST_R6_R0_8 130400F9
-DEFINE P1_ST_R6_R3_8 730400F9
-DEFINE P1_ST_R7_R0_0 140000F9
-DEFINE P1_ST_R7_R0_16 140800F9
-DEFINE P1_ST_R7_R3_16 740800F9
-
-## ---- Seed-Lisp step 4 extensions (tranche 10): reader + display --
-DEFINE P1_MOV_R1_R0 E10300AA
-DEFINE P1_MOV_R1_R2 E10302AA
-DEFINE P1_MOV_R1_R7 E10314AA
-DEFINE P1_MOV_R2_R1 E20301AA
-DEFINE P1_MOV_R6_R2 F30302AA
-DEFINE P1_MOV_R7_R1 F40301AA
-DEFINE P1_ADDI_R0_R0_NEG1 000400D1
-DEFINE P1_ADDI_R0_R0_NEG48 00C000D1
-DEFINE P1_ADDI_R1_R1_48 21C00091
-DEFINE P1_ADDI_R1_R1_NEG1 210400D1
-DEFINE P1_ADDI_R2_R2_8 42200091
-DEFINE P1_ADDI_R2_R2_NEG5 421400D1
-DEFINE P1_ADDI_R6_R6_NEG1 730600D1
-DEFINE P1_SARI_R1_R1_3 21FC4393
-DEFINE P1_SHLI_R0_R6_3 60F27DD3
-DEFINE P1_SHLI_R1_R6_3 61F27DD3
-DEFINE P1_SHLI_R2_R6_1 62FA7FD3
-DEFINE P1_SHLI_R3_R3_16 63BC70D3
-DEFINE P1_SHRI_R3_R3_16 63FC50D3
-DEFINE P1_ADD_R6_R1_R2 3300028B
-DEFINE P1_ADD_R6_R6_R0 7302008B
-DEFINE P1_ADD_R7_R1_R2 3400028B
-DEFINE P1_SUB_R2_R1_R6 220013CB
-DEFINE P1_SUB_R3_R1_R6 230013CB
-DEFINE P1_REM_R1_R1_R2 300CC29A0186029B
-DEFINE P1_BEQ_R0_R1 1F0001EB4100005420021FD6
-DEFINE P1_BEQ_R1_R2 3F0002EB4100005420021FD6
-DEFINE P1_BEQ_R1_R3 3F0003EB4100005420021FD6
-DEFINE P1_BEQ_R2_R1 5F0001EB4100005420021FD6
-DEFINE P1_BEQ_R6_R1 7F0201EB4100005420021FD6
-DEFINE P1_BNE_R7_R1 9F0201EB4000005420021FD6
-DEFINE P1_LB_R0_R2_0 40004039
-DEFINE P1_LD_R2_R1_0 220040F9
-DEFINE P1_LD_R2_R2_0 420040F9
-DEFINE P1_SB_R1_R2_0 41000039
-DEFINE P1_SB_R1_R6_0 61020039
-DEFINE P1_ST_R0_R3_8 600400F9
-DEFINE P1_ST_R2_R1_0 220000F9
-DEFINE P1_ST_R2_R3_24 620C00F9
diff --git a/p1_amd64.M1 b/p1_amd64.M1
@@ -1,238 +0,0 @@
-## p1_amd64.M1 — GENERATED by p1_gen.py. Do not edit by hand.
-##
-## Shared op-table lives in p1_gen.py; each arch's encoders expand
-## (op, register-tuple, imm) rows into native bytes. See P1.md for the
-## ISA spec and register mapping.
-
-
-## ---- LI — load 4-byte zero-extended literal from inline data slot
-DEFINE P1_LI_R0 B8
-DEFINE P1_LI_R1 BF
-DEFINE P1_LI_R2 BE
-DEFINE P1_LI_R3 BA
-DEFINE P1_LI_R4 41BD
-DEFINE P1_LI_R5 41BE
-DEFINE P1_LI_R6 BB
-DEFINE P1_LI_R7 41BC
-DEFINE P1_LI_BR 41BB
-
-## ---- SYSCALL / SYSOPEN — uniform (clobbers r0 only) across arches
-DEFINE P1_SYSCALL 4D89EA4D89F04989D90F05
-DEFINE P1_SYSOPEN B8020000000F05
-
-## ---- Linux syscall numbers (per-arch table). LE-32 immediate operands for LI.
-DEFINE SYS_WRITE 01000000
-DEFINE SYS_EXIT 3C000000
-DEFINE SYS_READ 00000000
-DEFINE SYS_CLOSE 03000000
-
-## ---- Reg-reg-reg arithmetic (tranche 1) --------------------------
-DEFINE P1_ADD_R1_R1_R2 4889FF4801F7
-DEFINE P1_ADD_R1_R1_R4 4889FF4C01EF
-DEFINE P1_ADD_R2_R2_R6 4889F64801DE
-DEFINE P1_ADD_R2_R3_R1 4889D64801FE
-DEFINE P1_SUB_R1_R1_R2 4889FF4829F7
-DEFINE P1_SUB_R2_R2_R6 4889F64829DE
-DEFINE P1_AND_R1_R1_R5 4889FF4C21F7
-DEFINE P1_OR_R1_R1_R2 4889FF4809F7
-DEFINE P1_XOR_R1_R1_R2 4889FF4831F7
-DEFINE P1_MUL_R1_R1_R2 4889FF480FAFFE
-DEFINE P1_DIV_R1_R1_R2 4989C34889D14889F8489948F7FE4889C74889CA4C89D8
-DEFINE P1_REM_R1_R1_R5 4989C34889D14889F8489949F7FE4889D74889CA4C89D8
-DEFINE P1_SHL_R1_R1_R2 4889FF4889F148D3E7
-DEFINE P1_SHR_R1_R1_R2 4889FF4889F148D3EF
-DEFINE P1_SAR_R4_R4_R2 4D89ED4889F149D3FD
-
-## ---- Immediate arithmetic (tranche 2) ----------------------------
-DEFINE P1_ADDI_R1_R1_3 4889FF4883C703
-DEFINE P1_ADDI_R1_R1_1 4889FF4883C701
-DEFINE P1_ADDI_R1_R1_NEG3 4889FF4883C7FD
-DEFINE P1_ADDI_R4_R4_NEG1 4D89ED4983C5FF
-DEFINE P1_ADDI_R1_R1_NEG2 4889FF4883C7FE
-DEFINE P1_ADDI_R0_R0_1 4889C04883C001
-DEFINE P1_SHLI_R1_R1_1 4889FF48C1E701
-DEFINE P1_SHRI_R1_R1_1 4889FF48C1EF01
-DEFINE P1_SARI_R4_R4_1 4D89ED49C1FD01
-DEFINE P1_ANDI_R1_R1_6 4889FF4883E706
-DEFINE P1_ANDI_R1_R1_7 4889FF4883E707
-DEFINE P1_ORI_R1_R1_1 4889FF4883CF01
-DEFINE P1_ORI_R0_R0_2 4889C04883C802
-DEFINE P1_ORI_R0_R0_7 4889C04883C807
-
-## ---- LA + memory ops (tranche 3) ---------------------------------
-DEFINE P1_LA_R4 41BD
-DEFINE P1_ST_R1_R4_0 49897D00
-DEFINE P1_LD_R1_R4_0 498B7D00
-DEFINE P1_ST_R1_R4_8 49897D08
-DEFINE P1_LD_R1_R4_8 498B7D08
-DEFINE P1_SB_R1_R4_16 49887D10
-DEFINE P1_LB_R1_R4_16 490FB67D10
-DEFINE P1_ST_R1_R4_NEG8 49897DF8
-DEFINE P1_LD_R1_R4_NEG8 498B7DF8
-
-## ---- Branches (tranche 4, LI_BR-indirect) ------------------------
-DEFINE P1_B 41FFE3
-DEFINE P1_BEQ_R2_R3 4839D6750341FFE3
-DEFINE P1_BNE_R2_R3 4839D6740341FFE3
-DEFINE P1_BLT_R2_R3 4839D67D0341FFE3
-DEFINE P1_BLT_R4_R2 4939F57D0341FFE3
-
-## ---- Control: CALL/RET + single-slot and N-slot PROLOGUE/EPILOGUE/TAIL
-DEFINE P1_PROLOGUE 594883EC1051
-DEFINE P1_EPILOGUE 594883C41051
-DEFINE P1_RET C3
-DEFINE P1_CALL 41FFD3
-DEFINE P1_TAIL 594883C4105141FFE3
-DEFINE P1_PROLOGUE_N2 594883EC2051
-DEFINE P1_EPILOGUE_N2 594883C42051
-DEFINE P1_TAIL_N2 594883C4205141FFE3
-DEFINE P1_PROLOGUE_N3 594883EC2051
-DEFINE P1_EPILOGUE_N3 594883C42051
-DEFINE P1_TAIL_N3 594883C4205141FFE3
-DEFINE P1_PROLOGUE_N4 594883EC3051
-DEFINE P1_EPILOGUE_N4 594883C43051
-DEFINE P1_TAIL_N4 594883C4305141FFE3
-
-## ---- Seed-Lisp step 1 extensions (tranche 6) ---------------------
-DEFINE P1_MOV_R1_R6 4889DF
-DEFINE P1_MOV_R6_R1 4889FB
-DEFINE P1_MOV_R6_R0 4889C3
-DEFINE P1_MOV_R0_R3 4889D0
-DEFINE P1_MOV_R7_R0 4989C4
-DEFINE P1_MOV_R7_R2 4989F4
-DEFINE P1_MOV_R2_R6 4889DE
-DEFINE P1_MOV_R3_R7 4C89E2
-DEFINE P1_MOV_R2_R7 4C89E6
-DEFINE P1_MOV_R4_R7 4D89E5
-DEFINE P1_MOV_R2_SP 4889E6
-DEFINE P1_MOV_R3_SP 4889E2
-DEFINE P1_MOV_R4_SP 4989E5
-DEFINE P1_MOV_R6_SP 4889E3
-DEFINE P1_MOV_R2_R0 4889C6
-DEFINE P1_LD_R0_R6_0 488B4300
-DEFINE P1_LD_R1_R6_16 488B7B10
-DEFINE P1_LD_R3_R4_0 498B5500
-DEFINE P1_LD_R0_R5_0 498B4600
-DEFINE P1_LB_R1_R4_0 490FB67D00
-DEFINE P1_ST_R2_R4_0 49897500
-DEFINE P1_ST_R0_R4_8 49894508
-DEFINE P1_LD_R0_R4_8 498B4508
-DEFINE P1_LB_R1_R0_0 480FB67800
-DEFINE P1_LD_R0_R1_0 488B4700
-DEFINE P1_LD_R0_R1_8 488B4708
-DEFINE P1_ST_R1_R0_0 48897800
-DEFINE P1_LD_R2_R4_0 498B7500
-DEFINE P1_ST_R2_R0_8 48897008
-DEFINE P1_LD_R0_R4_0 498B4500
-DEFINE P1_ST_R2_R4_16 49897510
-DEFINE P1_LD_R2_R4_16 498B7510
-DEFINE P1_LD_R0_R3_0 488B4200
-DEFINE P1_ST_R2_R3_0 48897200
-DEFINE P1_ST_R1_R3_8 48897A08
-DEFINE P1_LD_R1_R3_8 488B7A08
-DEFINE P1_ST_R2_R3_16 48897210
-DEFINE P1_LD_R2_R3_16 488B7210
-DEFINE P1_LD_R1_R1_0 488B7F00
-DEFINE P1_ADD_R2_R0_R1 4889C64801FE
-DEFINE P1_BLT_R0_R2 4839F07D0341FFE3
-DEFINE P1_BLT_R1_R2 4839F77D0341FFE3
-DEFINE P1_BNE_R1_R2 4839F7740341FFE3
-DEFINE P1_BNE_R0_R2 4839F0740341FFE3
-
-## ---- Seed-Lisp step 3 extensions (tranche 9): strings + interning
-DEFINE P1_MOV_R0_SP 4889E0
-DEFINE P1_MOV_R1_R3 4889D7
-DEFINE P1_ADDI_R1_R7_7 4C89E74883C707
-DEFINE P1_ADDI_R1_R1_8 4889FF4883C708
-DEFINE P1_ADDI_R1_R1_NEG5 4889FF4883C7FB
-DEFINE P1_ADDI_R2_R2_1 4889F64883C601
-DEFINE P1_ADDI_R2_R2_NEG1 4889F64883C6FF
-DEFINE P1_ADDI_R3_R0_8 4889C24883C208
-DEFINE P1_ADDI_R3_R3_1 4889D24883C201
-DEFINE P1_ADDI_R3_R3_NEG1 4889D24883C2FF
-DEFINE P1_ADDI_R6_R6_1 4889DB4883C301
-DEFINE P1_ADDI_R7_R7_NEG1 4D89E44983C4FF
-DEFINE P1_SHLI_R0_R0_3 4889C048C1E003
-DEFINE P1_SHLI_R0_R0_52 4889C048C1E034
-DEFINE P1_SHLI_R1_R1_3 4889FF48C1E703
-DEFINE P1_SHLI_R3_R0_5 4889C248C1E205
-DEFINE P1_SHLI_R6_R6_32 4889DB48C1E320
-DEFINE P1_SHRI_R0_R0_52 4889C048C1E834
-DEFINE P1_SHRI_R1_R1_3 4889FF48C1EF03
-DEFINE P1_SHRI_R6_R6_32 4889DB48C1EB20
-DEFINE P1_ORI_R0_R0_4 4889C04883C804
-DEFINE P1_ORI_R0_R0_1 4889C04883C801
-DEFINE P1_ADD_R0_R0_R3 4889C04801D0
-DEFINE P1_ADD_R2_R2_R0 4889F64801C6
-DEFINE P1_ADD_R2_R2_R1 4889F64801FE
-DEFINE P1_SUB_R3_R3_R0 4889D24829C2
-DEFINE P1_BEQ_R0_R6 4839D8750341FFE3
-DEFINE P1_BEQ_R2_R6 4839DE750341FFE3
-DEFINE P1_BEQ_R3_R1 4839FA750341FFE3
-DEFINE P1_BEQ_R3_R6 4839DA750341FFE3
-DEFINE P1_BEQ_R7_R1 4939FC750341FFE3
-DEFINE P1_BNE_R0_R1 4839F8740341FFE3
-DEFINE P1_BNE_R0_R6 4839D8740341FFE3
-DEFINE P1_BNE_R0_R7 4C39E0740341FFE3
-DEFINE P1_BNE_R6_R3 4839D3740341FFE3
-DEFINE P1_LB_R0_R1_0 480FB64700
-DEFINE P1_LB_R2_R6_0 480FB67300
-DEFINE P1_LB_R7_R2_0 4C0FB66600
-DEFINE P1_LD_R0_R2_0 488B4600
-DEFINE P1_LD_R0_R3_24 488B4218
-DEFINE P1_LD_R1_R3_24 488B7A18
-DEFINE P1_LD_R3_R2_0 488B5600
-DEFINE P1_LD_R6_R1_0 488B5F00
-DEFINE P1_LD_R6_R3_8 488B5A08
-DEFINE P1_LD_R7_R3_16 4C8B6210
-DEFINE P1_SB_R1_R0_7 48887807
-DEFINE P1_SB_R2_R3_0 48887200
-DEFINE P1_ST_R0_R2_0 48894600
-DEFINE P1_ST_R0_R3_24 48894218
-DEFINE P1_ST_R0_R4_0 49894500
-DEFINE P1_ST_R6_R0_8 48895808
-DEFINE P1_ST_R6_R3_8 48895A08
-DEFINE P1_ST_R7_R0_0 4C896000
-DEFINE P1_ST_R7_R0_16 4C896010
-DEFINE P1_ST_R7_R3_16 4C896210
-
-## ---- Seed-Lisp step 4 extensions (tranche 10): reader + display --
-DEFINE P1_MOV_R1_R0 4889C7
-DEFINE P1_MOV_R1_R2 4889F7
-DEFINE P1_MOV_R1_R7 4C89E7
-DEFINE P1_MOV_R2_R1 4889FE
-DEFINE P1_MOV_R6_R2 4889F3
-DEFINE P1_MOV_R7_R1 4989FC
-DEFINE P1_ADDI_R0_R0_NEG1 4889C04883C0FF
-DEFINE P1_ADDI_R0_R0_NEG48 4889C04883C0D0
-DEFINE P1_ADDI_R1_R1_48 4889FF4883C730
-DEFINE P1_ADDI_R1_R1_NEG1 4889FF4883C7FF
-DEFINE P1_ADDI_R2_R2_8 4889F64883C608
-DEFINE P1_ADDI_R2_R2_NEG5 4889F64883C6FB
-DEFINE P1_ADDI_R6_R6_NEG1 4889DB4883C3FF
-DEFINE P1_SARI_R1_R1_3 4889FF48C1FF03
-DEFINE P1_SHLI_R0_R6_3 4889D848C1E003
-DEFINE P1_SHLI_R1_R6_3 4889DF48C1E703
-DEFINE P1_SHLI_R2_R6_1 4889DE48C1E601
-DEFINE P1_SHLI_R3_R3_16 4889D248C1E210
-DEFINE P1_SHRI_R3_R3_16 4889D248C1EA10
-DEFINE P1_ADD_R6_R1_R2 4889FB4801F3
-DEFINE P1_ADD_R6_R6_R0 4889DB4801C3
-DEFINE P1_ADD_R7_R1_R2 4989FC4901F4
-DEFINE P1_SUB_R2_R1_R6 4889FE4829DE
-DEFINE P1_SUB_R3_R1_R6 4889FA4829DA
-DEFINE P1_REM_R1_R1_R2 4989C34889D14889F8489948F7FE4889D74889CA4C89D8
-DEFINE P1_BEQ_R0_R1 4839F8750341FFE3
-DEFINE P1_BEQ_R1_R2 4839F7750341FFE3
-DEFINE P1_BEQ_R1_R3 4839D7750341FFE3
-DEFINE P1_BEQ_R2_R1 4839FE750341FFE3
-DEFINE P1_BEQ_R6_R1 4839FB750341FFE3
-DEFINE P1_BNE_R7_R1 4939FC740341FFE3
-DEFINE P1_LB_R0_R2_0 480FB64600
-DEFINE P1_LD_R2_R1_0 488B7700
-DEFINE P1_LD_R2_R2_0 488B7600
-DEFINE P1_SB_R1_R2_0 48887E00
-DEFINE P1_SB_R1_R6_0 48887B00
-DEFINE P1_ST_R0_R3_8 48894208
-DEFINE P1_ST_R2_R1_0 48897700
-DEFINE P1_ST_R2_R3_24 48897218
diff --git a/p1_riscv64.M1 b/p1_riscv64.M1
@@ -1,238 +0,0 @@
-## p1_riscv64.M1 — GENERATED by p1_gen.py. Do not edit by hand.
-##
-## Shared op-table lives in p1_gen.py; each arch's encoders expand
-## (op, register-tuple, imm) rows into native bytes. See P1.md for the
-## ISA spec and register mapping.
-
-
-## ---- LI — load 4-byte zero-extended literal from inline data slot
-DEFINE P1_LI_R0 170500000365C5006F008000
-DEFINE P1_LI_R1 9705000083E5C5006F008000
-DEFINE P1_LI_R2 170600000366C6006F008000
-DEFINE P1_LI_R3 9706000083E6C6006F008000
-DEFINE P1_LI_R4 170A0000036ACA006F008000
-DEFINE P1_LI_R5 970A000083EACA006F008000
-DEFINE P1_LI_R6 9704000083E4C4006F008000
-DEFINE P1_LI_R7 170900000369C9006F008000
-DEFINE P1_LI_BR 170F0000036FCF006F008000
-
-## ---- SYSCALL / SYSOPEN — uniform (clobbers r0 only) across arches
-DEFINE P1_SYSCALL 9308050093890500130B0600938B06001385090093050B0013860B0093060A0013870A0093870400730000009385090013060B0093860B00
-DEFINE P1_SYSOPEN 1305C0F99308800373000000
-
-## ---- Linux syscall numbers (per-arch table). LE-32 immediate operands for LI.
-DEFINE SYS_WRITE 40000000
-DEFINE SYS_EXIT 5D000000
-DEFINE SYS_READ 3F000000
-DEFINE SYS_CLOSE 39000000
-
-## ---- Reg-reg-reg arithmetic (tranche 1) --------------------------
-DEFINE P1_ADD_R1_R1_R2 B385C500
-DEFINE P1_ADD_R1_R1_R4 B3854501
-DEFINE P1_ADD_R2_R2_R6 33069600
-DEFINE P1_ADD_R2_R3_R1 3386B600
-DEFINE P1_SUB_R1_R1_R2 B385C540
-DEFINE P1_SUB_R2_R2_R6 33069640
-DEFINE P1_AND_R1_R1_R5 B3F55501
-DEFINE P1_OR_R1_R1_R2 B3E5C500
-DEFINE P1_XOR_R1_R1_R2 B3C5C500
-DEFINE P1_MUL_R1_R1_R2 B385C502
-DEFINE P1_DIV_R1_R1_R2 B3C5C502
-DEFINE P1_REM_R1_R1_R5 B3E55503
-DEFINE P1_SHL_R1_R1_R2 B395C500
-DEFINE P1_SHR_R1_R1_R2 B3D5C500
-DEFINE P1_SAR_R4_R4_R2 335ACA40
-
-## ---- Immediate arithmetic (tranche 2) ----------------------------
-DEFINE P1_ADDI_R1_R1_3 93853500
-DEFINE P1_ADDI_R1_R1_1 93851500
-DEFINE P1_ADDI_R1_R1_NEG3 9385D5FF
-DEFINE P1_ADDI_R4_R4_NEG1 130AFAFF
-DEFINE P1_ADDI_R1_R1_NEG2 9385E5FF
-DEFINE P1_ADDI_R0_R0_1 13051500
-DEFINE P1_SHLI_R1_R1_1 93951500
-DEFINE P1_SHRI_R1_R1_1 93D51500
-DEFINE P1_SARI_R4_R4_1 135A1A40
-DEFINE P1_ANDI_R1_R1_6 93F56500
-DEFINE P1_ANDI_R1_R1_7 93F57500
-DEFINE P1_ORI_R1_R1_1 93E51500
-DEFINE P1_ORI_R0_R0_2 13652500
-DEFINE P1_ORI_R0_R0_7 13657500
-
-## ---- LA + memory ops (tranche 3) ---------------------------------
-DEFINE P1_LA_R4 170A0000036ACA006F008000
-DEFINE P1_ST_R1_R4_0 2330BA00
-DEFINE P1_LD_R1_R4_0 83350A00
-DEFINE P1_ST_R1_R4_8 2334BA00
-DEFINE P1_LD_R1_R4_8 83358A00
-DEFINE P1_SB_R1_R4_16 2308BA00
-DEFINE P1_LB_R1_R4_16 83450A01
-DEFINE P1_ST_R1_R4_NEG8 233CBAFE
-DEFINE P1_LD_R1_R4_NEG8 83358AFF
-
-## ---- Branches (tranche 4, LI_BR-indirect) ------------------------
-DEFINE P1_B 67000F00
-DEFINE P1_BEQ_R2_R3 6314D60067000F00
-DEFINE P1_BNE_R2_R3 6304D60067000F00
-DEFINE P1_BLT_R2_R3 6354D60067000F00
-DEFINE P1_BLT_R4_R2 6354CA0067000F00
-
-## ---- Control: CALL/RET + single-slot and N-slot PROLOGUE/EPILOGUE/TAIL
-DEFINE P1_PROLOGUE 130101FF23301100
-DEFINE P1_EPILOGUE 8330010013010101
-DEFINE P1_RET 67800000
-DEFINE P1_CALL E7000F00
-DEFINE P1_TAIL 833001001301010167000F00
-DEFINE P1_PROLOGUE_N2 130101FE23301100
-DEFINE P1_EPILOGUE_N2 8330010013010102
-DEFINE P1_TAIL_N2 833001001301010267000F00
-DEFINE P1_PROLOGUE_N3 130101FE23301100
-DEFINE P1_EPILOGUE_N3 8330010013010102
-DEFINE P1_TAIL_N3 833001001301010267000F00
-DEFINE P1_PROLOGUE_N4 130101FD23301100
-DEFINE P1_EPILOGUE_N4 8330010013010103
-DEFINE P1_TAIL_N4 833001001301010367000F00
-
-## ---- Seed-Lisp step 1 extensions (tranche 6) ---------------------
-DEFINE P1_MOV_R1_R6 93850400
-DEFINE P1_MOV_R6_R1 93840500
-DEFINE P1_MOV_R6_R0 93040500
-DEFINE P1_MOV_R0_R3 13850600
-DEFINE P1_MOV_R7_R0 13090500
-DEFINE P1_MOV_R7_R2 13090600
-DEFINE P1_MOV_R2_R6 13860400
-DEFINE P1_MOV_R3_R7 93060900
-DEFINE P1_MOV_R2_R7 13060900
-DEFINE P1_MOV_R4_R7 130A0900
-DEFINE P1_MOV_R2_SP 13060100
-DEFINE P1_MOV_R3_SP 93060100
-DEFINE P1_MOV_R4_SP 130A0100
-DEFINE P1_MOV_R6_SP 93040100
-DEFINE P1_MOV_R2_R0 13060500
-DEFINE P1_LD_R0_R6_0 03B50400
-DEFINE P1_LD_R1_R6_16 83B50401
-DEFINE P1_LD_R3_R4_0 83360A00
-DEFINE P1_LD_R0_R5_0 03B50A00
-DEFINE P1_LB_R1_R4_0 83450A00
-DEFINE P1_ST_R2_R4_0 2330CA00
-DEFINE P1_ST_R0_R4_8 2334AA00
-DEFINE P1_LD_R0_R4_8 03358A00
-DEFINE P1_LB_R1_R0_0 83450500
-DEFINE P1_LD_R0_R1_0 03B50500
-DEFINE P1_LD_R0_R1_8 03B58500
-DEFINE P1_ST_R1_R0_0 2330B500
-DEFINE P1_LD_R2_R4_0 03360A00
-DEFINE P1_ST_R2_R0_8 2334C500
-DEFINE P1_LD_R0_R4_0 03350A00
-DEFINE P1_ST_R2_R4_16 2338CA00
-DEFINE P1_LD_R2_R4_16 03360A01
-DEFINE P1_LD_R0_R3_0 03B50600
-DEFINE P1_ST_R2_R3_0 23B0C600
-DEFINE P1_ST_R1_R3_8 23B4B600
-DEFINE P1_LD_R1_R3_8 83B58600
-DEFINE P1_ST_R2_R3_16 23B8C600
-DEFINE P1_LD_R2_R3_16 03B60601
-DEFINE P1_LD_R1_R1_0 83B50500
-DEFINE P1_ADD_R2_R0_R1 3306B500
-DEFINE P1_BLT_R0_R2 6354C50067000F00
-DEFINE P1_BLT_R1_R2 63D4C50067000F00
-DEFINE P1_BNE_R1_R2 6384C50067000F00
-DEFINE P1_BNE_R0_R2 6304C50067000F00
-
-## ---- Seed-Lisp step 3 extensions (tranche 9): strings + interning
-DEFINE P1_MOV_R0_SP 13050100
-DEFINE P1_MOV_R1_R3 93850600
-DEFINE P1_ADDI_R1_R7_7 93057900
-DEFINE P1_ADDI_R1_R1_8 93858500
-DEFINE P1_ADDI_R1_R1_NEG5 9385B5FF
-DEFINE P1_ADDI_R2_R2_1 13061600
-DEFINE P1_ADDI_R2_R2_NEG1 1306F6FF
-DEFINE P1_ADDI_R3_R0_8 93068500
-DEFINE P1_ADDI_R3_R3_1 93861600
-DEFINE P1_ADDI_R3_R3_NEG1 9386F6FF
-DEFINE P1_ADDI_R6_R6_1 93841400
-DEFINE P1_ADDI_R7_R7_NEG1 1309F9FF
-DEFINE P1_SHLI_R0_R0_3 13153500
-DEFINE P1_SHLI_R0_R0_52 13154503
-DEFINE P1_SHLI_R1_R1_3 93953500
-DEFINE P1_SHLI_R3_R0_5 93165500
-DEFINE P1_SHLI_R6_R6_32 93940402
-DEFINE P1_SHRI_R0_R0_52 13554503
-DEFINE P1_SHRI_R1_R1_3 93D53500
-DEFINE P1_SHRI_R6_R6_32 93D40402
-DEFINE P1_ORI_R0_R0_4 13654500
-DEFINE P1_ORI_R0_R0_1 13651500
-DEFINE P1_ADD_R0_R0_R3 3305D500
-DEFINE P1_ADD_R2_R2_R0 3306A600
-DEFINE P1_ADD_R2_R2_R1 3306B600
-DEFINE P1_SUB_R3_R3_R0 B386A640
-DEFINE P1_BEQ_R0_R6 6314950067000F00
-DEFINE P1_BEQ_R2_R6 6314960067000F00
-DEFINE P1_BEQ_R3_R1 6394B60067000F00
-DEFINE P1_BEQ_R3_R6 6394960067000F00
-DEFINE P1_BEQ_R7_R1 6314B90067000F00
-DEFINE P1_BNE_R0_R1 6304B50067000F00
-DEFINE P1_BNE_R0_R6 6304950067000F00
-DEFINE P1_BNE_R0_R7 6304250167000F00
-DEFINE P1_BNE_R6_R3 6384D40067000F00
-DEFINE P1_LB_R0_R1_0 03C50500
-DEFINE P1_LB_R2_R6_0 03C60400
-DEFINE P1_LB_R7_R2_0 03490600
-DEFINE P1_LD_R0_R2_0 03350600
-DEFINE P1_LD_R0_R3_24 03B58601
-DEFINE P1_LD_R1_R3_24 83B58601
-DEFINE P1_LD_R3_R2_0 83360600
-DEFINE P1_LD_R6_R1_0 83B40500
-DEFINE P1_LD_R6_R3_8 83B48600
-DEFINE P1_LD_R7_R3_16 03B90601
-DEFINE P1_SB_R1_R0_7 A303B500
-DEFINE P1_SB_R2_R3_0 2380C600
-DEFINE P1_ST_R0_R2_0 2330A600
-DEFINE P1_ST_R0_R3_24 23BCA600
-DEFINE P1_ST_R0_R4_0 2330AA00
-DEFINE P1_ST_R6_R0_8 23349500
-DEFINE P1_ST_R6_R3_8 23B49600
-DEFINE P1_ST_R7_R0_0 23302501
-DEFINE P1_ST_R7_R0_16 23382501
-DEFINE P1_ST_R7_R3_16 23B82601
-
-## ---- Seed-Lisp step 4 extensions (tranche 10): reader + display --
-DEFINE P1_MOV_R1_R0 93050500
-DEFINE P1_MOV_R1_R2 93050600
-DEFINE P1_MOV_R1_R7 93050900
-DEFINE P1_MOV_R2_R1 13860500
-DEFINE P1_MOV_R6_R2 93040600
-DEFINE P1_MOV_R7_R1 13890500
-DEFINE P1_ADDI_R0_R0_NEG1 1305F5FF
-DEFINE P1_ADDI_R0_R0_NEG48 130505FD
-DEFINE P1_ADDI_R1_R1_48 93850503
-DEFINE P1_ADDI_R1_R1_NEG1 9385F5FF
-DEFINE P1_ADDI_R2_R2_8 13068600
-DEFINE P1_ADDI_R2_R2_NEG5 1306B6FF
-DEFINE P1_ADDI_R6_R6_NEG1 9384F4FF
-DEFINE P1_SARI_R1_R1_3 93D53540
-DEFINE P1_SHLI_R0_R6_3 13953400
-DEFINE P1_SHLI_R1_R6_3 93953400
-DEFINE P1_SHLI_R2_R6_1 13961400
-DEFINE P1_SHLI_R3_R3_16 93960601
-DEFINE P1_SHRI_R3_R3_16 93D60601
-DEFINE P1_ADD_R6_R1_R2 B384C500
-DEFINE P1_ADD_R6_R6_R0 B384A400
-DEFINE P1_ADD_R7_R1_R2 3389C500
-DEFINE P1_SUB_R2_R1_R6 33869540
-DEFINE P1_SUB_R3_R1_R6 B3869540
-DEFINE P1_REM_R1_R1_R2 B3E5C502
-DEFINE P1_BEQ_R0_R1 6314B50067000F00
-DEFINE P1_BEQ_R1_R2 6394C50067000F00
-DEFINE P1_BEQ_R1_R3 6394D50067000F00
-DEFINE P1_BEQ_R2_R1 6314B60067000F00
-DEFINE P1_BEQ_R6_R1 6394B40067000F00
-DEFINE P1_BNE_R7_R1 6304B90067000F00
-DEFINE P1_LB_R0_R2_0 03450600
-DEFINE P1_LD_R2_R1_0 03B60500
-DEFINE P1_LD_R2_R2_0 03360600
-DEFINE P1_SB_R1_R2_0 2300B600
-DEFINE P1_SB_R1_R6_0 2380B400
-DEFINE P1_ST_R0_R3_8 23B4A600
-DEFINE P1_ST_R2_R1_0 23B0C500
-DEFINE P1_ST_R2_R3_24 23BCC600
