asm_06_temp_boundary.c (695B)
1 /* Register constraints are properties of this asm boundary, not of a value's 2 * entire allocated live range. In particular, ARM r0-r3 and RISC-V t4-t6 are 3 * optimizer-emitter temp banks: explicit pins and restricted constraint sets 4 * must be satisfied by instruction-local staging without escaping into MIR. */ 5 6 int test_main(void) { 7 #if defined(__arm__) 8 register long pinned __asm__("r0") = 40; 9 long low = 2; 10 __asm__ volatile("add r0, r0, %1" : "+r"(pinned) : "l"(low)); 11 return (int)pinned; 12 #elif defined(__riscv) && __riscv_xlen == 64 13 register long pinned __asm__("t6") = 40; 14 __asm__ volatile("addi t6, t6, 2" : "+r"(pinned)); 15 return (int)pinned; 16 #else 17 return 42; 18 #endif 19 }