ibit_shift_var.c (724B)
1 /* 32-bit shifts by a variable amount. On aarch64 these lower to the 2 * variable-shift register forms: LSLV, LSRV, ASRV. volatile on both the value 3 * and the shift count keeps the register form live (no folding to an immediate 4 * shift). 5 * u = 0x15 (21), sh1 = 1: u << 1 = 42 (logical left) 6 * v = 0x150 (336), sh3 = 3: v >> 3 = 42 (logical right, unsigned) 7 * s = -336, sh3 = 3: s >> 3 = -42 (arithmetic right, signed) 8 * 42 + 42 + (-42) = 42. */ 9 int test_main(void) { 10 volatile unsigned int u = 0x15; 11 volatile unsigned int v = 0x150; 12 volatile int s = -336; 13 volatile int sh1 = 1, sh3 = 3; 14 int lsl = (int)(u << sh1); 15 int lsr = (int)(v >> sh3); 16 int asr = s >> sh3; 17 return lsl + lsr + asr; 18 }