kit

aa64_sweep_gen.c (2817B)

---

 /* aa64_sweep_gen — emit one representative encoding per row of aa64_insn_table
  * (as little-endian hex words), for the asm<->disasm self-symmetry round-trip
  * (test/asm/symmetry.sh).
  *
  * The harness decodes each word, re-assembles the disassembly, and decodes
  * again, asserting the text is a fixed point. That catches the two decode-side
  * asymmetries the codegen round-trip can't reach systematically: a form the
  * disassembler decodes but the assembler can't re-encode (assemble error), and
  * a form where decode and encode disagree on the bytes (text changes across the
  * round-trip). All decode/encode goes through asm-runner, so the comparison is
  * immune to any formatting difference between rendering paths.
  *
  * Variable (~mask) bits are filled with a fixed representative pattern that
  * gives distinct, non-ZR/SP registers in the standard field positions; the
  * text-fixed-point criterion tolerates the resulting don't-care bits (e.g. the
  * RES Rt2 field of an exclusive load). Formats whose only operand is a
  * PC-relative target or a relocation — branches and adr/adrp — are skipped:
  * they aren't assemblable standalone without a label/symbol, and L1/L2 of the
  * codegen round-trip already cover them.
  *
  * Builds against the internal arch/aa64/isa.h surface (mk/test.mk passes
  * -Isrc).
  */
 
 #include <stdint.h>
 #include <stdio.h>
 
 #include "arch/aa64/isa.h"
 
 static int needs_context(uint8_t fmt) {
   switch (fmt) {
     case AA64_FMT_BR_IMM:    /* b/bl: numeric target needs a label */
     case AA64_FMT_BR_COND:   /* b.cc */
     case AA64_FMT_CB:        /* cbz/cbnz */
     case AA64_FMT_PCREL_ADR: /* adr/adrp: needs a symbol operand */
       return 1;
     default:
       return 0;
   }
 }
 
 int main(void) {
   /* Rt/Rd[4:0]=1, Rn[9:5]=2, Rt2/Ra[14:10]=3, Rm/Rs[20:16]=4 — distinct,
    * non-ZR/SP so ZR-keyed aliases don't fire; small immediates elsewhere. */
   const uint32_t PATTERN = (1u << 0) | (2u << 5) | (3u << 10) | (4u << 16);
   for (uint32_t i = 0; i < aa64_insn_table_n; ++i) {
     const AA64InsnDesc* d = &aa64_insn_table[i];
     uint32_t word;
     if (needs_context(d->fmt)) continue;
     word = (d->match & d->mask) | (PATTERN & ~d->mask);
     /* The register-offset form's option field [15:13] must name a valid
      * extend; the bare fill pattern yields the invalid UXTB(000). Force
      * LSL/UXTX(011) so the synthesized word is a real instruction. */
     if (d->fmt == AA64_FMT_LDST_REGOFF)
       word = (word & ~(7u << 13)) | (3u << 13);
     /* Only sweep words that decode cleanly to this kind of instruction. */
     if (!aa64_disasm_find(word)) continue;
     printf("%02x%02x%02x%02x\n", (unsigned)(word & 0xff),
            (unsigned)((word >> 8) & 0xff), (unsigned)((word >> 16) & 0xff),
            (unsigned)((word >> 24) & 0xff));
   }
   return 0;
 }