reloc_riscv32.c (5188B)
1 /* RelocKind <-> RISC-V ELF reloc-type mapping (ELFCLASS32 / RV32 ILP32*). 2 * 3 * Clone of reloc_riscv64.c. The RISC-V reloc type codes are XLEN-neutral 4 * and fit in the 8-bit ELF32 r_info type field, so every code-relative / 5 * data-relative kind is reused verbatim. The only divergences are the 6 * 64-bit-wide kinds: 7 * - R_ABS64 -> unsupported on RV32 (ELF_R_RISCV_NONE) 8 * - R_RV_ADD64 / R_RV_SUB64 -> unsupported on RV32 (ELF_R_RISCV_NONE) 9 * and, on the read side, ELF_R_RISCV_64 / ADD64 / SUB64 map to the 10 * (u32)-1 sentinel so the reader diagnoses them rather than silently 11 * fabricating a 64-bit RelocKind for a 32-bit object. 12 * 13 * R_ABS32 -> ELF_R_RISCV_32 is the RV32 primary absolute reloc. */ 14 15 #include "obj/elf/elf.h" 16 17 u32 elf_riscv32_reloc_to(u32 kind /* RelocKind */) { 18 switch (kind) { 19 case R_NONE: 20 return ELF_R_RISCV_NONE; 21 /* R_ABS64 / R_RV_ADD64 / R_RV_SUB64 are 64-bit-only: unsupported on 22 * RV32 (fall through to NONE so emit_elf flags them). */ 23 case R_ABS32: 24 return ELF_R_RISCV_32; 25 case R_PC32: 26 return ELF_R_RISCV_32_PCREL; 27 case R_RV_HI20: 28 return ELF_R_RISCV_HI20; 29 case R_RV_LO12_I: 30 return ELF_R_RISCV_LO12_I; 31 case R_RV_LO12_S: 32 return ELF_R_RISCV_LO12_S; 33 case R_RV_BRANCH: 34 return ELF_R_RISCV_BRANCH; 35 case R_RV_JAL: 36 return ELF_R_RISCV_JAL; 37 case R_RV_CALL: 38 return ELF_R_RISCV_CALL; 39 case R_PLT32: 40 return ELF_R_RISCV_CALL_PLT; 41 case R_RV_PCREL_HI20: 42 return ELF_R_RISCV_PCREL_HI20; 43 case R_RV_PCREL_LO12_I: 44 return ELF_R_RISCV_PCREL_LO12_I; 45 case R_RV_PCREL_LO12_S: 46 return ELF_R_RISCV_PCREL_LO12_S; 47 case R_RV_GOT_HI20: 48 return ELF_R_RISCV_GOT_HI20; 49 case R_RV_TLS_GOT_HI20: 50 return ELF_R_RISCV_TLS_GOT_HI20; 51 case R_RV_TPREL_HI20: 52 return ELF_R_RISCV_TPREL_HI20; 53 case R_RV_TPREL_LO12_I: 54 return ELF_R_RISCV_TPREL_LO12_I; 55 case R_RV_TPREL_LO12_S: 56 return ELF_R_RISCV_TPREL_LO12_S; 57 case R_RV_TPREL_ADD: 58 return ELF_R_RISCV_TPREL_ADD; 59 case R_ADD8: 60 return ELF_R_RISCV_ADD8; 61 case R_ADD16: 62 return ELF_R_RISCV_ADD16; 63 case R_ADD32: 64 return ELF_R_RISCV_ADD32; 65 case R_SUB8: 66 return ELF_R_RISCV_SUB8; 67 case R_SUB16: 68 return ELF_R_RISCV_SUB16; 69 case R_SUB32: 70 return ELF_R_RISCV_SUB32; 71 case R_RV_ALIGN: 72 return ELF_R_RISCV_ALIGN; 73 case R_RV_RVC_BRANCH: 74 return ELF_R_RISCV_RVC_BRANCH; 75 case R_RV_RVC_JUMP: 76 return ELF_R_RISCV_RVC_JUMP; 77 case R_RV_RELAX: 78 return ELF_R_RISCV_RELAX; 79 case R_SUB6: 80 return ELF_R_RISCV_SUB6; 81 case R_SET6: 82 return ELF_R_RISCV_SET6; 83 case R_ABS8: 84 return ELF_R_RISCV_SET8; 85 case R_ABS16: 86 return ELF_R_RISCV_SET16; 87 case R_SET_ULEB128: 88 return ELF_R_RISCV_SET_ULEB128; 89 case R_SUB_ULEB128: 90 return ELF_R_RISCV_SUB_ULEB128; 91 default: 92 return ELF_R_RISCV_NONE; 93 } 94 } 95 96 u32 elf_riscv32_reloc_from(u32 elf_type) { 97 switch (elf_type) { 98 case ELF_R_RISCV_NONE: 99 return R_NONE; 100 /* ELF_R_RISCV_64 / ADD64 / SUB64 are 64-bit-only: not valid in an 101 * ELFCLASS32 object — fall through to the (u32)-1 sentinel. */ 102 case ELF_R_RISCV_32: 103 return R_ABS32; 104 case ELF_R_RISCV_32_PCREL: 105 return R_PC32; 106 case ELF_R_RISCV_HI20: 107 return R_RV_HI20; 108 case ELF_R_RISCV_LO12_I: 109 return R_RV_LO12_I; 110 case ELF_R_RISCV_LO12_S: 111 return R_RV_LO12_S; 112 case ELF_R_RISCV_BRANCH: 113 return R_RV_BRANCH; 114 case ELF_R_RISCV_JAL: 115 return R_RV_JAL; 116 case ELF_R_RISCV_CALL: 117 return R_RV_CALL; 118 case ELF_R_RISCV_CALL_PLT: 119 return R_PLT32; 120 case ELF_R_RISCV_PCREL_HI20: 121 return R_RV_PCREL_HI20; 122 case ELF_R_RISCV_PCREL_LO12_I: 123 return R_RV_PCREL_LO12_I; 124 case ELF_R_RISCV_PCREL_LO12_S: 125 return R_RV_PCREL_LO12_S; 126 case ELF_R_RISCV_GOT_HI20: 127 return R_RV_GOT_HI20; 128 case ELF_R_RISCV_TLS_GOT_HI20: 129 return R_RV_TLS_GOT_HI20; 130 case ELF_R_RISCV_TPREL_HI20: 131 return R_RV_TPREL_HI20; 132 case ELF_R_RISCV_TPREL_LO12_I: 133 return R_RV_TPREL_LO12_I; 134 case ELF_R_RISCV_TPREL_LO12_S: 135 return R_RV_TPREL_LO12_S; 136 case ELF_R_RISCV_TPREL_ADD: 137 return R_RV_TPREL_ADD; 138 case ELF_R_RISCV_ADD8: 139 return R_ADD8; 140 case ELF_R_RISCV_ADD16: 141 return R_ADD16; 142 case ELF_R_RISCV_ADD32: 143 return R_ADD32; 144 case ELF_R_RISCV_SUB8: 145 return R_SUB8; 146 case ELF_R_RISCV_SUB16: 147 return R_SUB16; 148 case ELF_R_RISCV_SUB32: 149 return R_SUB32; 150 case ELF_R_RISCV_ALIGN: 151 return R_RV_ALIGN; 152 case ELF_R_RISCV_RVC_BRANCH: 153 return R_RV_RVC_BRANCH; 154 case ELF_R_RISCV_RVC_JUMP: 155 return R_RV_RVC_JUMP; 156 case ELF_R_RISCV_RELAX: 157 return R_RV_RELAX; 158 case ELF_R_RISCV_SUB6: 159 return R_SUB6; 160 case ELF_R_RISCV_SET6: 161 return R_SET6; 162 case ELF_R_RISCV_SET8: 163 return R_ABS8; 164 case ELF_R_RISCV_SET16: 165 return R_ABS16; 166 case ELF_R_RISCV_SET32: 167 return R_ABS32; 168 case ELF_R_RISCV_SET_ULEB128: 169 return R_SET_ULEB128; 170 case ELF_R_RISCV_SUB_ULEB128: 171 return R_SUB_ULEB128; 172 default: 173 return (u32)-1; /* sentinel */ 174 } 175 }