kit

native_direct_target.h (11425B)

---

 #ifndef KIT_CG_NATIVE_DIRECT_TARGET_H
 #define KIT_CG_NATIVE_DIRECT_TARGET_H
 
 #include "arch/native_target.h"
 #include "cg/cgtarget.h"
 
 /* NativeDirectTarget is the shared direct -O0 implementation of CgTarget for
  * native backends. It owns semantic local homes, direct-mode scratch policy,
  * local register caching, and conservative flushes. Arch code supplies a
  * NativeTarget plus this small adapter for ABI/frame/legality decisions. */
 
 typedef struct NativeDirectTarget NativeDirectTarget;
 
 typedef struct NativeDirectScope {
   u8 kind; /* ScopeKind */
   u8 owns_break;
   u8 pad[2];
   Label break_label;
   Label continue_label;
 } NativeDirectScope;
 
 typedef enum NativeDirectBarrier {
   NATIVE_DIRECT_BARRIER_CALL = 1u << 0,
   NATIVE_DIRECT_BARRIER_MEMORY = 1u << 1,
   NATIVE_DIRECT_BARRIER_VOLATILE = 1u << 2,
   NATIVE_DIRECT_BARRIER_ATOMIC = 1u << 3,
   NATIVE_DIRECT_BARRIER_INLINE_ASM = 1u << 4,
 } NativeDirectBarrier;
 
 typedef struct NativeDirectLocal {
   KitCgTypeId type;
   u32 size;
   u32 align;
   u32 flags; /* CGLocalFlag */
 
   NativeFrameSlot home;
   Reg reg;
   u8 cls; /* NativeAllocClass */
   u8 dirty;
   u8 address_taken;
   u8 memory_required;
   u8 transient; /* a per-subexpression temp; its home is reclaimable at a
                  * statement boundary (see nd_reclaim_temps) */
   /* The cached register holds this local's value zero-extended to the full
    * register, straight from a narrow integer load (ldrb/ldrh/ldr-w always zero
    * the upper bits). While set, a CV_ZEXT widening it is a no-op and is elided
    * by nd_convert. Set only in nd_load; cleared on any other write
    * (nd_dst_writeback) and when the register is dropped (flush/invalidate).
    * Meaningful only while reg != REG_NONE. */
   u8 load_zext;
   /* The cached register holds this local's value SIGN-extended to the full
    * register, from an MF_SEXT_LOAD narrow load that the backend honored with a
    * sign-extending load (aa64 ldrsb/ldrsh, gated on load_sext). While set, a
    * CV_SEXT widening it to any wider integer is a no-op and is elided by
    * nd_convert. Set only in nd_load; cleared exactly like load_zext (a spill +
    * plain reload would zero-extend, so clearing it forces the real extend to run
    * on the reloaded value — see nd_flush_local / nd_invalidate_local). */
   u8 load_sext;
   u32 last_use; /* d->use_tick at the most recent cache touch (LRU victim key)
                  */
   /* Intrusive doubly-linked list of currently-cached locals, in insertion
    * (caching) order so nd_cache_link is O(1) tail insertion. Values are 0-based
    * indices into NativeDirectTarget.locals (or -1); only valid while this local
    * is cached (l->reg != REG_NONE). */
   i32 cache_next;
   i32 cache_prev;
 } NativeDirectLocal;
 
 typedef enum NativeDirectAddrLegality {
   NATIVE_DIRECT_ADDR_ILLEGAL,
   NATIVE_DIRECT_ADDR_LEGAL,
   NATIVE_DIRECT_ADDR_LEGAL_IF_UNSCALED,
 } NativeDirectAddrLegality;
 
 typedef struct NativeOps NativeOps;
 /* Semantic-only adapter the arch supplies on the NDT path. `ops` is mandatory:
  * aa64_backend_make and aa64_semantic_target_new always pass it. Pure
  * pass-throughs to NativeTarget (reg_info, func_begin/func_end, frame-slot
  * allocation, class_for_type, addr_legal) are not mirrored here -- NDT calls
  * d->native->X directly for those. */
 struct NativeOps {
   void (*bind_param)(NativeDirectTarget*, const CGParamDesc*, CGLocal,
                      NativeDirectLocal*);
 
   int (*operand_legal)(NativeDirectTarget*, const Operand*, NativeAllocClass);
   NativeDirectAddrLegality (*semantic_addr_legal)(NativeDirectTarget*,
                                                   Operand addr, MemAccess);
 
   void (*marshal_call)(NativeDirectTarget*, const NativeCallDesc*,
                        NativeCallPhase*);
   const char* (*tail_call_unrealizable_reason)(NativeDirectTarget*,
                                                const CGCallDesc*);
   void (*emit_call)(NativeDirectTarget*, const NativeCallPhase*);
   /* `value` is the single returned local, or CG_LOCAL_NONE for void. */
   void (*emit_ret)(NativeDirectTarget*, CGLocal value);
 
   void (*va_start_)(NativeDirectTarget*, Operand ap_addr);
   void (*va_arg_)(NativeDirectTarget*, Operand dst, Operand ap_addr,
                   KitCgTypeId type);
   void (*va_end_)(NativeDirectTarget*, Operand ap_addr);
   void (*va_copy_)(NativeDirectTarget*, Operand dst_ap_addr,
                    Operand src_ap_addr);
 
   void (*asm_block)(NativeDirectTarget*, const char* tmpl,
                     const AsmConstraint* outs, u32 nout, Operand* out_ops,
                     const AsmConstraint* ins, u32 nin, const Operand* in_ops,
                     const Sym* clobbers, u32 nclob, u32 clobber_abi_sets);
 
   void (*barrier)(NativeDirectTarget*, u32 flags);
 };
 
 /* Fixed transient buffers for per-op location/label arrays (call args/results,
  * return values, intrinsic operands, indirect-branch targets). The common case
  * fits these and allocates nothing; overflow falls back to the TU arena. */
 #define ND_ARG_BUF 16u
 #define ND_RET_BUF 8u
 #define ND_LBL_BUF 16u
 
 typedef struct NativeDirectTargetConfig {
   NativeTarget* native;
   const NativeOps* ops;
   void* user;
   u32 flags;
 } NativeDirectTargetConfig;
 
 struct NativeDirectTarget {
   CgTarget base;
   u32 magic;
   NativeTarget* native;
   const NativeOps* ops;
   void* user;
 
   /* Register info and per-class info resolved once at construction (constant
    * for the program), so scratch acquire / cache alloc / evict do an O(1)
    * lookup instead of re-resolving reg_info and linearly scanning ri->classes.
    */
   const NativeRegInfo* reg_info;
   const NativeAllocClassInfo* class_info[NATIVE_REG_CLASS_COUNT];
 
   /* Per-class -O0 value-cache register pool, precomputed at construction in
    * `allocable[]` order. On ndt_caller_saved_only targets (aa64) it is the
    * caller-saved subset of allocable, so the deferred prologue never has to
    * spill a callee-save. Other targets take the whole allocable list: their NDT
    * allocable sets are deliberately hazard-free (no implicit-clobber registers
    * such as the x86 shift/divide regs) and any callee-save among them is either
    * covered by the reserve_callee_saves prologue path (x64 r13-r15, whose save
    * region is fixed-size) or is itself caller-saved (riscv a-regs), so caching
    * in them is both safe and free of a single-pass prologue-budget blowup.
    * Note: `allocable[]` is read only by the NDT, never the optimizer (which
    * allocates over the phys[] ALLOCABLE flags), so each arch tunes it for -O0
    * register caching independently of -O1. */
   Reg cache_pool[NATIVE_REG_CLASS_COUNT][NATIVE_MAX_HARD_REGS];
   u32 ncache_pool[NATIVE_REG_CLASS_COUNT];
 
   const CGFuncDesc* func;
   SrcLoc loc;
 
   NativeDirectLocal* locals;
   u32 nlocals;
   u32 locals_cap;
 
   /* Transient temp locals minted since the last reclaim (statement boundary), in
    * allocation order. nd_reclaim_temps drains this to invalidate their cache
    * entries and return their frame homes to the free list; bounded by one
    * statement's temp depth. */
   CGLocal* transient_locals;
   u32 ntransient;
   u32 transient_cap;
 
   MCLabel* labels;
   u32 nlabels;
   u32 labels_cap;
 
   NativeDirectScope* scopes;
   u32 nscopes;
   u32 scopes_cap;
 
   u32 scratch_used[NATIVE_REG_CLASS_COUNT];
   /* Per-function callee-saved registers borrowed by direct scratch/cache
    * allocation. Reported to the native backend before prologue patching. */
   u32 callee_saved_used[NATIVE_REG_CLASS_COUNT];
   /* Local register cache (write-back, basic-block-scoped). reg_owner[cls][reg]
    * names the semantic local currently cached in that physical register, or
    * CG_LOCAL_NONE. scratch_used doubles as the per-class "pinned for the
    * current instruction" mask. Per-local cache state (reg/cls/dirty) lives on
    * NativeDirectLocal. See doc/CODEGEN.md "local register cache". */
   CGLocal reg_owner[NATIVE_REG_CLASS_COUNT][NATIVE_MAX_HARD_REGS];
   u32 use_tick; /* monotonic counter stamped onto NativeDirectLocal.last_use */
   /* Flat mirror of the currently-owning local's last_use, keyed by physical
    * register, so the LRU victim scan reads one contiguous array instead of
    * chasing a NativeDirectLocal per candidate. Written by nd_touch_local
    * whenever an owned register's last_use changes; only read for registers with
    * reg_owner[cls][reg] != CG_LOCAL_NONE, where it equals that local's
    * last_use. */
   u32 reg_last_use[NATIVE_REG_CLASS_COUNT][NATIVE_MAX_HARD_REGS];
   /* Head/tail of the intrusive cached-locals list (in caching order), -1 when
    * empty; ncached is its length. Lets nd_flush_all run in O(cached) instead of
    * scanning all nlocals on every control-flow / barrier op; cache_tail makes
    * nd_cache_link an O(1) tail insertion. */
   i32 cache_head;
   i32 cache_tail;
   u32 ncached;
   u32 max_outgoing;
 
   /* Transient per-op buffers; see ND_*_BUF. Inputs use argbuf, outputs retbuf;
    * never live across more than one op, so reuse between ops is safe. */
   NativeLoc argbuf[ND_ARG_BUF];
   NativeLoc retbuf[ND_RET_BUF];
   MCLabel lblbuf[ND_LBL_BUF];
 
   ObjSecId local_static_sec;
   ObjSymId local_static_sym;
   u32 local_static_base;
   u32 local_static_size;
   u8 local_static_active;
 };
 
 CgTarget* native_direct_target_new(Compiler*, ObjBuilder*,
                                    const NativeDirectTargetConfig*);
 NativeTarget* native_direct_target_native(CgTarget*);
 
 /* Per-arch NativeTarget constructor, e.g. aa64_native_target_new. */
 typedef NativeTarget* (*NativeTargetCtor)(Compiler*, ObjBuilder*, MCEmitter*);
 
 /* Shared glue for an ArchImpl's backend.make hook. Builds the MCEmitter +
  * optional Debug producer (cg_mc_debug_new), constructs the arch NativeTarget
  * via `ctor`, then wraps it in a NativeDirectTarget configured with `ops`.
  * Returns NULL on any failure. Each arch backend_make is exactly a call to
  * this with its own (ctor, ops). */
 CgTarget* native_direct_backend_make(Compiler*, ObjBuilder*,
                                      const KitCodeOptions*,
                                      NativeTargetCtor ctor,
                                      const NativeOps* ops);
 
 /* Shared glue for an ArchImpl's cgtarget_new hook (semantic/assembler path).
  * Reuses the caller's MCEmitter when non-NULL, else mints one with mc_new; no
  * Debug producer. Constructs the arch NativeTarget via `ctor` and wraps it in a
  * NativeDirectTarget configured with `ops`. Returns NULL on any failure. */
 CgTarget* native_direct_semantic_target_new(Compiler*, ObjBuilder*, MCEmitter*,
                                             NativeTargetCtor ctor,
                                             const NativeOps* ops);
 
 /* Project a semantic CGCallDesc into a NativeCallDesc whose args/results are
  * the callee's incoming frame slots (the layout a sibling/tail call must land
  * in). `nd` is fully overwritten (memset to zero, then its args/results buffers
  * are arena-allocated from d->locals[*].home). This is the arch-neutral core
  * the per-arch tail_call_unrealizable_reason hooks share; each backend wraps it
  * with its own eligibility guards and call_stack_size / incoming-window
  * comparison. Leaves nd.callee / flags / tail_policy / inline_policy zeroed. */
 void native_direct_project_tail_call_desc(NativeDirectTarget* d,
                                           const CGCallDesc* call,
                                           NativeCallDesc* nd);
 
 #endif