link.c (6810B)
1 /* RV64 link-time arch descriptor. See link_arch.h for the contract. 2 * 3 * The PLT0/PLT-entry/IPLT-stub byte layouts here mirror what used to 4 * live inline in link_dyn.c (PLT) and link_layout.c (IPLT) before the 5 * vtable refactor; comments preserve the WHY (notably the +0x800 bias 6 * on AUIPC immediates). */ 7 8 #include "arch/riscv/isa.h" 9 #include "core/bytes.h" 10 #include "core/core.h" 11 #include "link/link_arch.h" 12 13 /* PLT0 is 8 canonical NOPs (32 bytes); each PLT entry and IPLT stub is 14 * 4 instructions (16 bytes) / 3 instructions (12 bytes) respectively. 15 * Encoded once here so the descriptor and emitters stay in sync. */ 16 #define RV64_PLT0_SIZE 32u 17 #define RV64_PLT_ENTRY_SIZE 16u 18 #define RV64_IPLT_STUB_SIZE 12u 19 20 /* Split a PC-relative displacement into the (hi20, lo12) pair consumed 21 * by the AUIPC + I-type sequence. The +0x800 bias is the standard 22 * RISC-V two-instruction PCREL trick: AUIPC adds an upper-20 immediate 23 * shifted left 12, then the second instruction adds a sign-extended 24 * 12-bit lo12. If we naively split disp into (disp>>12, disp&0xfff) 25 * the lo12 sign-extends as a *negative* number whenever bit 11 is set, 26 * which underflows the AUIPC result by 0x1000. Adding 0x800 before 27 * the shift rounds the high half up in exactly the cases that need it 28 * so AUIPC + sign-extended-lo12 reconstructs disp correctly. */ 29 static inline void rv64_split_pcrel(i64 disp, u32* hi20_out, u32* lo12_out) { 30 *hi20_out = (u32)(((u64)(disp + 0x800)) >> 12) & 0xfffffu; 31 *lo12_out = (u32)((u64)disp & 0xfffu); 32 } 33 34 /* PLT0 under DF_1_NOW is never executed — the loader resolves every 35 * JUMP_SLOT before transferring control — but we still emit it in 36 * canonical form (8 NOPs) so disassemblers and unwinders see a well- 37 * formed prologue at the top of .plt. */ 38 static void rv64_emit_plt0(u8* dst, u64 plt0_vaddr, u64 gotplt_vaddr) { 39 u32 i; 40 (void)plt0_vaddr; 41 (void)gotplt_vaddr; 42 for (i = 0; i < RV64_PLT0_SIZE; i += 4u) wr_u32_le(dst + i, rv_nop()); 43 } 44 45 /* Per-import PLT entry: load the GOT slot pre-filled by the loader 46 * (R_RISCV_JUMP_SLOT) and tail-call through it. t1 is the standard 47 * psABI scratch for the trampoline return-address (clobbered by the 48 * lazy resolver in the non-BIND_NOW path); t3 holds the slot pointer. */ 49 /* Load a GOT/.igot.plt slot into `reg`: 8-byte slot (LD) on RV64, 4-byte 50 * slot (LW) on RV32. The only XLEN-divergent instruction in the PLT/IPLT. */ 51 static u32 rv_load_slot(u32 reg, i32 imm12, int xlen8) { 52 return xlen8 ? rv_ld(reg, reg, imm12) : rv_lw(reg, reg, imm12); 53 } 54 55 /* Per-import PLT entry (shared rv64/rv32): load the GOT slot pre-filled by 56 * the loader (R_RISCV_JUMP_SLOT) and tail-call through it. t1 is the standard 57 * psABI scratch for the trampoline return address (clobbered by the lazy 58 * resolver in the non-BIND_NOW path); t3 holds the slot pointer. 16 bytes / 59 * 4 insns; the AUIPC + (hi20,lo12) split is XLEN-neutral. */ 60 static void rv_emit_plt_entry(u8* dst, u64 entry_vaddr, u64 slot_vaddr, 61 int xlen8) { 62 i64 disp = (i64)slot_vaddr - (i64)entry_vaddr; 63 u32 hi20; 64 u32 lo12; 65 rv64_split_pcrel(disp, &hi20, &lo12); 66 wr_u32_le(dst + 0, rv_auipc(RV_T3, hi20)); 67 wr_u32_le(dst + 4, rv_load_slot(RV_T3, (i32)lo12, xlen8)); 68 wr_u32_le(dst + 8, rv_jalr(RV_T1, RV_T3, 0)); 69 wr_u32_le(dst + 12, rv_nop()); 70 } 71 72 /* IPLT stub (shared rv64/rv32): load .igot.plt[i] (filled at startup by the 73 * resolver) and tail-call to it. The stub->slot displacement is invariant 74 * under the segment-base shift (both addresses live in the same image), so we 75 * bake it directly into the instructions and report zero apply-time relocs — 76 * unlike aarch64, which cannot encode a 32-bit pcrel inline. 12 bytes / 3 77 * insns. */ 78 static u32 rv_emit_iplt_stub(u8* dst, u64 stub_vaddr, u64 slot_vaddr, 79 int xlen8) { 80 i64 disp = (i64)slot_vaddr - (i64)stub_vaddr; 81 u32 hi20; 82 u32 lo12; 83 rv64_split_pcrel(disp, &hi20, &lo12); 84 wr_u32_le(dst + 0, rv_auipc(RV_T1, hi20)); 85 wr_u32_le(dst + 4, rv_load_slot(RV_T1, (i32)lo12, xlen8)); 86 wr_u32_le(dst + 8, rv_jr(RV_T1)); 87 return 0u; 88 } 89 90 static void rv64_emit_plt_entry(u8* dst, u64 entry_vaddr, u64 slot_vaddr) { 91 rv_emit_plt_entry(dst, entry_vaddr, slot_vaddr, 1); 92 } 93 static void rv32_emit_plt_entry(u8* dst, u64 entry_vaddr, u64 slot_vaddr) { 94 rv_emit_plt_entry(dst, entry_vaddr, slot_vaddr, 0); 95 } 96 static u32 rv64_emit_iplt_stub(u8* dst, u64 stub_vaddr, u64 slot_vaddr, 97 LinkArchIPltReloc out[2]) { 98 (void)out; 99 return rv_emit_iplt_stub(dst, stub_vaddr, slot_vaddr, 1); 100 } 101 static u32 rv32_emit_iplt_stub(u8* dst, u64 stub_vaddr, u64 slot_vaddr, 102 LinkArchIPltReloc out[2]) { 103 (void)out; 104 return rv_emit_iplt_stub(dst, stub_vaddr, slot_vaddr, 0); 105 } 106 107 /* Width + classification rows for RISC-V's relocation kinds (shared by rv64 108 * and rv32); defined in src/arch/riscv/reloc.c and consulted through the 109 * .reloc_desc hook. R_RV_CALL / R_PLT32 carry RELOC_IS_BRANCH: a direct 110 * AUIPC+JALR reaches only ±2GiB, so a too-far target (e.g. a JIT-resolved 111 * host libc symbol) routes through the call-stub pass, the same safety net 112 * aa64 and x64 wire. rv_reloc_apply_insn (same file) holds the matching 113 * U/I/S/B/J + RVC instruction-immediate byte encoders. */ 114 const RelocDesc* rv_reloc_desc(RelocKind); 115 int rv_reloc_apply_insn(Compiler*, RelocKind, u8*, u64, i64, u64); 116 void rv_jit_tls_le_relax(Compiler*, RelocKind, u8*, u64, u64); 117 int rv_jit_reloc_relax(Compiler*, RelocKind, const JitRelaxCtx*); 118 119 const LinkArchDesc link_arch_rv64 = { 120 .plt0_size = RV64_PLT0_SIZE, 121 .plt_entry_size = RV64_PLT_ENTRY_SIZE, 122 .iplt_stub_size = RV64_IPLT_STUB_SIZE, 123 .global_pointer_symbol = "__global_pointer$", 124 .global_pointer_rw_offset = 0x800u, 125 .emit_plt0 = rv64_emit_plt0, 126 .emit_plt_entry = rv64_emit_plt_entry, 127 .emit_iplt_stub = rv64_emit_iplt_stub, 128 .reloc_desc = rv_reloc_desc, 129 .reloc_apply_insn = rv_reloc_apply_insn, 130 .jit_tls_le_relax = rv_jit_tls_le_relax, 131 .jit_reloc_relax = rv_jit_reloc_relax, 132 }; 133 134 /* RV32 link descriptor: identical to rv64 (PLT0/entry/stub byte sizes, 135 * __global_pointer$ + 0x800 RW bias, canonical 8-NOP PLT0, and the JIT 136 * call-stub predicate) EXCEPT the PLT/IPLT emitters load 4-byte GOT 137 * slots with LW instead of LD. */ 138 const LinkArchDesc link_arch_rv32 = { 139 .plt0_size = RV64_PLT0_SIZE, 140 .plt_entry_size = RV64_PLT_ENTRY_SIZE, 141 .iplt_stub_size = RV64_IPLT_STUB_SIZE, 142 .global_pointer_symbol = "__global_pointer$", 143 .global_pointer_rw_offset = 0x800u, 144 .emit_plt0 = rv64_emit_plt0, 145 .emit_plt_entry = rv32_emit_plt_entry, 146 .emit_iplt_stub = rv32_emit_iplt_stub, 147 .reloc_desc = rv_reloc_desc, 148 .reloc_apply_insn = rv_reloc_apply_insn, 149 .jit_reloc_relax = rv_jit_reloc_relax, 150 };