kit

native_target.h (27597B)

---

 #ifndef KIT_ARCH_NATIVE_TARGET_H
 #define KIT_ARCH_NATIVE_TARGET_H
 
 #include <string.h>
 
 #include "arch/mc.h"
 #include "cg/cgtarget.h"
 #include "cg/type.h"
 #include "core/core.h"
 #include "core/slice.h" /* Slice, for resolve_name */
 
 /* NativeTarget is the physical native-emission contract. It is driven after
  * semantic CG has been either direct-lowered by NativeDirectTarget or recorded,
  * optimized, machinized, and allocated. It must not speak in semantic CGLocal
  * ids except where a descriptor is carried for diagnostics or ABI queries. */
 
 typedef u32 NativeFrameSlot;
 #define NATIVE_FRAME_SLOT_NONE 0u
 
 typedef enum NativeFrameSlotKind {
   NATIVE_FRAME_SLOT_LOCAL,
   NATIVE_FRAME_SLOT_PARAM,
   NATIVE_FRAME_SLOT_SPILL,
   NATIVE_FRAME_SLOT_ALLOCA,
   NATIVE_FRAME_SLOT_OUTGOING,
   NATIVE_FRAME_SLOT_SAVE,
 } NativeFrameSlotKind;
 
 typedef enum NativeFrameSlotFlag {
   NATIVE_FRAME_SLOT_NONE_FLAG = 0,
   NATIVE_FRAME_SLOT_ADDR_TAKEN = 1u << 0,
   NATIVE_FRAME_SLOT_MEMORY_REQUIRED = 1u << 1,
   NATIVE_FRAME_SLOT_FIXED_OFFSET = 1u << 2,
 } NativeFrameSlotFlag;
 
 typedef struct NativeFrameSlotDesc {
   KitCgTypeId type;
   Sym name;
   SrcLoc loc;
   u32 size;
   u32 align;
   i32 fixed_offset;
   u8 kind; /* NativeFrameSlotKind */
   u8 pad;
   u16 flags; /* NativeFrameSlotFlag */
 } NativeFrameSlotDesc;
 
 typedef struct NativeKnownFrameDesc {
   const NativeFrameSlotDesc* slots;
   u32 nslots;
   u32 max_outgoing;
   u32 align;
   /* Callee-saved hard registers the allocator assigned, one bitmask per
    * NativeAllocClass (indexed by class id). The backend reserves a save slot
    * and emits the prologue save / epilogue restore for each — equivalent to a
    * reserve_callee_saves() call, but folded into the known-frame setup so the
    * full frame is fixed before the prologue is emitted. NULL / 0 means none. */
   const u32* callee_saved_used;
   u32 ncallee_classes;
   /* Union of the clobber register names of every inline-asm block in the body.
    * Inline-asm clobbers are invisible to the operand scan that builds
    * callee_saved_used, so the optimizer forwards the raw names here and the
    * backend resolves them with its own clobber parser, folding the callee-saved
    * ones into its save set (applying its ABI predicate, which excludes the
    * frame pointer and keeps any reserved-but-callee-saved scratch such as x64
    * rbx). The prologue/epilogue then preserve them, so the asm hook needs no
    * per-block spill — which on the known-frame path would request a frame slot
    * after the frame is already final. NULL / 0 when the body contains no inline
    * asm. */
   const Sym* asm_clobbers;
   u32 nasm_clobbers;
   /* Union of KitCgAsmClobberAbiSet bits over the body's inline-asm blocks: an
    * arch-neutral "clobbers the whole caller/callee-saved set" the backend
    * expands against its own register file, alongside the named asm_clobbers. */
   u32 asm_clobber_abi_sets;
   /* Whether the function body contains a dynamic alloca. The backend needs this
    * up front (before the body) to decide prologue/epilogue form, since with a
    * known frame the slim-epilogue eligibility is settled at func_begin. */
   u8 has_alloca;
   /* Whether the body has an operation that needs a backend-internal scratch
    * spill slot — on aa64, an atomic read-modify-write, whose retry loop spills
    * one scratch register. The backend reserves the slot up front so the body
    * never grows the frame after the prologue. */
   u8 needs_scratch_spill;
   /* Whether the function is a leaf — its body contains no call of any kind
    * (regular or sibling/tail). A leaf does not clobber the return-address
    * register or the stack below sp through a call, so backends can omit the
    * saved-frame record entirely (rv64 leaf tier) or skip the stack reservation
    * and keep locals in the red zone (x64 SysV red-zone tier) — but ONLY when
    * `has_asm` is also clear (see below). Conservatively false whenever any
    * IR_CALL is present. */
   u8 is_leaf;
   /* Whether the body contains an inline-asm block. Inline asm can clobber the
    * return-address register (rv64 ra) or write into the red zone / make a call
    * (x64) without the optimizer modelling it, so the frame-eliding
    * leaf/red-zone tiers must NOT fire when this is set — even for an
    * otherwise-leaf function. The single-pass and fat known-frame shapes always
    * save the return address and reserve their stack, so they are unaffected. */
   u8 has_asm;
   /* Whether the body reads its own frame-pointer chain via
    * __builtin_frame_address / __builtin_return_address (INTRIN_FRAME_ADDRESS /
    * INTRIN_RETURN_ADDRESS). Such a function must keep a valid frame record and
    * frame pointer, so the frameless-leaf tier (rv64 slim_prologue, which emits
    * no prologue and never anchors s0) must NOT fire. aa64/x64 keep the frame
    * record in every prologue shape, so they ignore this flag. */
   u8 reads_frame;
 } NativeKnownFrameDesc;
 
 typedef enum NativeAllocClass {
   NATIVE_REG_INT,
   NATIVE_REG_FP,
   NATIVE_REG_VEC,
 } NativeAllocClass;
 
 typedef enum NativeRegFlag {
   NATIVE_REG_NONE = 0,
   NATIVE_REG_ALLOCABLE = 1u << 0,
   NATIVE_REG_CALLER_SAVED = 1u << 1,
   NATIVE_REG_CALLEE_SAVED = 1u << 2,
   NATIVE_REG_ARG = 1u << 3,
   NATIVE_REG_RET = 1u << 4,
   NATIVE_REG_RESERVED = 1u << 5,
   NATIVE_REG_TEMP_PREFERRED = 1u << 6,
 } NativeRegFlag;
 
 typedef struct NativePhysRegInfo {
   Reg reg;
   u8 cls;       /* NativeAllocClass */
   u8 abi_index; /* 0xff when not an ordered ABI arg/ret register */
   u16 flags;    /* NativeRegFlag */
   u16 spill_cost;
   u16 copy_cost;
 } NativePhysRegInfo;
 
 typedef struct NativeAllocClassInfo {
   u8 cls; /* NativeAllocClass */
   u8 pad[3];
 
   const Reg* allocable;
   u32 nallocable;
 
   const Reg* scratch;
   u32 nscratch;
 
   const NativePhysRegInfo* phys;
   u32 nphys;
 
   u32 caller_saved_mask;
   u32 callee_saved_mask;
   u32 arg_mask;
   u32 ret_mask;
   u32 reserved_mask;
 } NativeAllocClassInfo;
 
 typedef struct NativeRegInfo NativeRegInfo;
 struct NativeRegInfo {
   const NativeAllocClassInfo* classes;
   u32 nclasses;
 
   /* Map a register name to its (Reg, class). `name` is the raw spelling
    * ("rax", "x8", "a7"); the caller resolves any Sym to its bytes first so this
    * stays pool-free. Returns 0 on success, non-zero for a non-register name. */
   int (*resolve_name)(const NativeRegInfo*, Slice name, Reg* out,
                       NativeAllocClass* cls_out);
   /* True when (cls, reg) is a valid hard-register home for an inline-asm value
    * operand. This is intentionally separate from allocator availability:
    * syscall idioms need ABI registers such as x8/a7, while stack/frame, zero,
    * link, platform, and backend scratch registers must stay unavailable even if
    * the assembler can name them. */
   int (*asm_operand_reg_ok)(const NativeRegInfo*, NativeAllocClass cls,
                             Reg reg);
   /* Optional target-specific register-constraint parser for inline asm. The
    * input is the constraint body after generic modifiers ('=', '+', '&') have
    * been stripped. Return non-zero only for constraints that name a register
    * class; set fixed_out to REG_NONE for a free class or to a physical register
    * when the constraint hard-wires the operand (x86 "a" -> rax). Set
    * allowed_mask_out to 0 for the whole class, or a physical-register bitmask
    * when the constraint names a restricted class subset. */
   int (*asm_constraint_reg)(const NativeRegInfo*, const char* body,
                             NativeAllocClass* cls_out, Reg* fixed_out,
                             u32* allowed_mask_out);
   const char* (*debug_name)(const NativeRegInfo*, NativeAllocClass, Reg);
   u32 (*dwarf_reg)(const NativeRegInfo*, NativeAllocClass, Reg);
 };
 
 typedef enum NativeLocKind {
   NATIVE_LOC_NONE,
   NATIVE_LOC_REG,
   NATIVE_LOC_FRAME,
   NATIVE_LOC_STACK,
   NATIVE_LOC_IMM,
   NATIVE_LOC_GLOBAL,
   NATIVE_LOC_ADDR,
 } NativeLocKind;
 
 typedef enum NativeAddrBaseKind {
   NATIVE_ADDR_BASE_NONE,
   NATIVE_ADDR_BASE_REG,
   NATIVE_ADDR_BASE_FRAME,
   NATIVE_ADDR_BASE_FRAME_VALUE,
   NATIVE_ADDR_BASE_GLOBAL,
 } NativeAddrBaseKind;
 
 typedef enum NativeAddrIndexKind {
   NATIVE_ADDR_INDEX_NONE,
   NATIVE_ADDR_INDEX_REG,
   NATIVE_ADDR_INDEX_FRAME_VALUE,
 } NativeAddrIndexKind;
 
 typedef enum NativeImmUse {
   NATIVE_IMM_MOVE,
   NATIVE_IMM_BINOP,
   NATIVE_IMM_CMP,
   NATIVE_IMM_ADDR_OFFSET,
 } NativeImmUse;
 
 typedef struct NativeAddr {
   u8 base_kind;  /* NativeAddrBaseKind */
   u8 cls;        /* NativeAllocClass for base value */
   u8 index_kind; /* NativeAddrIndexKind */
   u8 index_cls;  /* NativeAllocClass for index value */
   u8 log2_scale;
   u8 pad[3];
   KitCgTypeId base_type;
   KitCgTypeId index_type;
   union {
     Reg reg;
     NativeFrameSlot frame;
     struct {
       ObjSymId sym;
       i64 addend;
     } global;
   } base;
   union {
     Reg reg;
     NativeFrameSlot frame;
   } index;
   i32 offset;
 } NativeAddr;
 
 typedef struct NativeLoc {
   u8 kind; /* NativeLocKind */
   u8 cls;  /* NativeAllocClass for register-like locations */
   u8 pad[2];
   KitCgTypeId type;
   union {
     Reg reg;
     NativeFrameSlot frame;
     struct {
       NativeFrameSlot slot;
       i32 offset;
     } stack;
     i64 imm;
     struct {
       ObjSymId sym;
       i64 addend;
     } global;
     NativeAddr addr;
   } v;
 } NativeLoc;
 
 typedef struct NativeInst NativeInst;
 
 typedef enum NativePatchKind {
   NATIVE_PATCH_FRAME_SIZE,
   NATIVE_PATCH_MAX_OUTGOING,
   NATIVE_PATCH_ARCH = 0x1000,
 } NativePatchKind;
 
 typedef struct NativePatch {
   u32 kind; /* NativePatchKind or arch-private */
   u32 section_id;
   u32 offset;
   u32 width;
   i64 addend;
   u64 value;
 } NativePatch;
 
 typedef struct NativeFramePatchState {
   u32 max_outgoing;
   u32 max_align;
 } NativeFramePatchState;
 
 #define NATIVE_CALL_PLAN_CLASSES 3u
 
 /* A semantic machine operation, enough for the target to report the physical
  * registers its encoding clobbers as a side effect (e.g. x86 idiv writes
  * rax/rdx, variable shifts use cl). Built by the optimizer from an instruction;
  * the descriptor keeps the backend from depending on the optimizer IR. */
 typedef enum NativeMachineOpKind {
   NATIVE_MOP_BINOP,
   NATIVE_MOP_VA_START,
   NATIVE_MOP_VA_ARG,
   NATIVE_MOP_ATOMIC_CAS,
   NATIVE_MOP_ATOMIC_RMW,
   NATIVE_MOP_INTRINSIC,
   /* A thread-local address materialization (IR_TLS_ADDR_OF). On targets whose
    * TLS access model uses fixed scratch/result registers or a resolver-thunk
    * call (e.g. Mach-O TLV descriptors → x0/x16/x17/lr), the encoding clobbers
    * those regs even though the IR op only declares its destination. Targets
    * whose TLS sequence touches only the destination register (ELF Local-Exec)
    * report no clobbers. */
   NATIVE_MOP_TLS_ADDR,
 } NativeMachineOpKind;
 
 typedef struct NativeMachineOp {
   u8 kind;          /* NativeMachineOpKind */
   u8 binop;         /* BinOp, when kind == NATIVE_MOP_BINOP */
   u8 intrin;        /* IntrinKind, when kind == NATIVE_MOP_INTRINSIC */
   u8 second_is_reg; /* binop's second operand is a register (not an immediate)
                      */
   u8 result_is_fp;  /* result lands in an FP register (e.g. va_arg of a double)
                      */
 } NativeMachineOp;
 
 typedef struct NativeCallDesc {
   KitCgTypeId fn_type;
   NativeLoc callee;
   const NativeLoc* args;
   const NativeLoc* results;
   u32 nargs;
   u32 nresults;
   u16 flags;      /* CGCallFlag */
   u8 tail_policy; /* KitCgTailPolicy */
   u8 pad;
   KitCgInlinePolicy inline_policy;
 } NativeCallDesc;
 
 typedef enum NativeCallPlanMoveKind {
   NATIVE_CALL_MOVE_NONE,
   NATIVE_CALL_MOVE_VALUE,
   NATIVE_CALL_MOVE_ADDR,
 } NativeCallPlanMoveKind;
 
 typedef struct NativeCallPlanMove {
   NativeLoc src;
   NativeLoc dst;
   MemAccess mem;
   u8 src_kind; /* NativeCallPlanMoveKind */
   u8 dst_kind; /* NativeLocKind */
   u8 pad[2];
 } NativeCallPlanMove;
 
 typedef struct NativeCallPlanRet {
   NativeLoc src;
   NativeLoc dst;
   MemAccess mem;
 } NativeCallPlanRet;
 
 typedef struct NativeCallPlan {
   NativeLoc callee;
   NativeCallPlanMove* args;
   NativeCallPlanRet* rets;
   u32 nargs;
   u32 nrets;
   u32 stack_arg_size;
   u32 clobber_mask[NATIVE_CALL_PLAN_CLASSES];
   u32 return_mask[NATIVE_CALL_PLAN_CLASSES];
   u16 flags; /* CGCallFlag */
   u8 has_sret;
   u8 is_variadic;
 } NativeCallPlan;
 
 typedef struct NativeTarget NativeTarget;
 struct NativeTarget {
   Compiler* c;
   ObjBuilder* obj;
   MCEmitter* mc;
   const NativeRegInfo* regs;
 
   NativeAllocClass (*class_for_type)(NativeTarget*, KitCgTypeId);
   int (*imm_legal)(NativeTarget*, NativeImmUse, u32 op, KitCgTypeId, i64);
   int (*addr_legal)(NativeTarget*, const NativeAddr*, MemAccess);
   /* Optional. Report the physical registers the target's encoding of `op`
    * clobbers as a side effect (not its declared operands/results), one bitmask
    * per NativeAllocClass. The optimizer keeps values live ACROSS the
    * instruction out of these registers, so the backend may use them freely (x86
    * idiv writes rax/rdx; a variable shift uses cl; atomics use rax/rcx/rdx).
    * Return non-zero if any register is clobbered, 0 otherwise (the common,
    * unconstrained case). NULL means no instruction clobbers fixed registers
    * (aa64/rv64). */
   int (*machine_op_clobbers)(NativeTarget*, const NativeMachineOp* op,
                              u32 clobber_mask[NATIVE_CALL_PLAN_CLASSES]);
 
   void (*func_begin)(NativeTarget*, const CGFuncDesc*);
   void (*func_begin_known_frame)(NativeTarget*, const CGFuncDesc*,
                                  const NativeKnownFrameDesc*,
                                  NativeFrameSlot* out_slots);
   void (*note_frame_state)(NativeTarget*, const NativeFramePatchState*);
   /* Optional. Called once after func_begin and before frame-slot mapping, with
    * the set of callee-saved hard registers the allocator assigned (one bitmask
    * per NativeAllocClass, indexed by class id). The target reserves save slots
    * and emits the prologue save / epilogue restore for each. Register
    * allocation is complete before emission, so the caller knows the full set
    * up front. */
   void (*reserve_callee_saves)(NativeTarget*, const u32* used_by_class,
                                u32 nclasses);
   /* Optional live-ABI caller/callee-saved register masks for a class. Static
    * NativeAllocClassInfo masks describe the target register file, but some
    * targets vary preservation rules by OS ABI (x64 SysV vs Win64 XMM regs).
    * The optimizer and direct emission use these to keep allocation, call
    * clobbers, and prologue save sets aligned with the selected ABI. NULL falls
    * back to NativeAllocClassInfo.{caller,callee}_saved_mask. */
   u32 (*caller_saved_mask)(NativeTarget*, NativeAllocClass);
   u32 (*callee_saved_mask)(NativeTarget*, NativeAllocClass);
   /* Optional. When set, the optimizer emit path calls this once — after
    * func_begin, reserve_callee_saves, and frame-slot mapping, but before the
    * body — to emit a minimal, exact-size prologue in place (no reserved NOP
    * region). Frame-size immediates are still patched in func_end, since the
    * final frame size isn't known until body emission allocates its temporaries.
    * Backends that leave this NULL fall back to the single-pass
    * reserve-and-patch prologue used by NativeDirectTarget. Gated by
    * `emit_minimal_prologue`, which the optimizer emit path sets before
    * func_begin so func_begin can skip the reserved region. */
   void (*emit_prologue)(NativeTarget*);
   u8 emit_minimal_prologue;
   /* Bytes of stack-passed arguments the fixed parameters of this function
    * signature use (the part beyond the register arg pools). Sets *variadic to
    * whether the signature is variadic and *nparams to the fixed parameter
    * count. Used to decide tail-call (sibling) realizability: the callee's
    * outgoing stack args must fit the area the caller itself received. Either
    * out-pointer may be NULL. May itself be NULL. */
   u32 (*signature_stack_bytes)(NativeTarget*, KitCgTypeId fn_type,
                                int* variadic, u32* nparams);
   /* Pure query: the outgoing stack-argument bytes a call with this descriptor
    * uses, rounded to the ABI's outgoing-area alignment. Reads only fn_type,
    * flags, nargs, and each args[i].type — never argument *locations* — so the
    * optimizer can call it in a frame-planning pre-pass, before any argument
    * marshalling is emitted, to size the outgoing area. Must equal the
    * stack_arg_size plan_call computes for the same descriptor. May be NULL. */
   u32 (*call_stack_bytes)(NativeTarget*, const NativeCallDesc*);
   /* Integer hardware zero register, if the ISA has one (aa64 wzr/xzr, rv64
    * x0). When `has_store_zero_reg` is set, the emit path stores a constant 0
    * straight from `store_zero_reg` instead of materializing 0 into a scratch
    * with a mov/movz first. */
   u8 has_store_zero_reg;
   Reg store_zero_reg;
   void (*func_end)(NativeTarget*);
 
   NativeFrameSlot (*frame_slot)(NativeTarget*, const NativeFrameSlotDesc*);
   /* Optional post-finalization query for a native frame slot's debug location.
    * Each arch owns the frame layout math and returns the coordinate system its
    * debugger/unwinder path can materialize. */
   int (*frame_slot_debug_loc)(NativeTarget*, NativeFrameSlot, CGDebugLoc*);
   /* Place the incoming parameter into `dst`. The caller (which has run register
    * allocation) chooses the destination: a hard register (NATIVE_LOC_REG) for a
    * register-allocated scalar param, a frame slot (NATIVE_LOC_FRAME) for an
    * address-taken / spilled / aggregate param. NATIVE_LOC_NONE means the param
    * is unused and only the ABI register/stack cursor must advance. Incoming arg
    * registers are never allocable, so reg destinations never alias an incoming
    * arg register and ordering across params is unconstrained. */
   void (*bind_param)(NativeTarget*, const CGParamDesc*, NativeLoc dst);
   /* Optional. Called once by the optimizer emit path after the last bind_param,
    * before the body. Lets a backend that defers register-destination param
    * binds (to resolve them as a parallel copy, since the allocator may rotate
    * params across the incoming arg registers — a permutation the naive
    * per-param move order cannot realize) flush them now. Backends that bind
    * eagerly leave this NULL. */
   void (*bind_params_end)(NativeTarget*);
 
   MCLabel (*label_new)(NativeTarget*);
   void (*label_place)(NativeTarget*, MCLabel);
   void (*jump)(NativeTarget*, MCLabel);
   void (*cmp_branch)(NativeTarget*, CmpOp, NativeLoc a, NativeLoc b,
                      MCLabel target);
   void (*indirect_branch)(NativeTarget*, NativeLoc addr,
                           const MCLabel* valid_targets, u32 ntargets);
   void (*load_label_addr)(NativeTarget*, NativeLoc dst, MCLabel target);
 
   void (*emit)(NativeTarget*, const NativeInst*);
   /* All instruction-emission hooks require caller-selected legal physical
    * operands. In particular, dst values are NATIVE_LOC_REG, arithmetic sources
    * are NATIVE_LOC_REG or target-legal immediates, and memory base/index
    * registers in NativeAddr must already be materialized. NativeTarget may
    * validate and assert, but it must not allocate registers. */
   void (*move)(NativeTarget*, NativeLoc dst_reg, NativeLoc src_reg);
   void (*load_imm)(NativeTarget*, NativeLoc dst_reg, i64 imm);
   void (*load_const)(NativeTarget*, NativeLoc dst_reg, ConstBytes);
   void (*load_addr)(NativeTarget*, NativeLoc dst_reg, NativeAddr addr);
   void (*load)(NativeTarget*, NativeLoc dst_reg, NativeAddr addr, MemAccess);
   void (*store)(NativeTarget*, NativeAddr addr, NativeLoc src_reg, MemAccess);
   void (*tls_addr_of)(NativeTarget*, NativeLoc dst_reg, ObjSymId sym,
                       i64 addend);
   void (*copy_bytes)(NativeTarget*, NativeAddr dst, NativeAddr src,
                      AggregateAccess);
   void (*set_bytes)(NativeTarget*, NativeAddr dst, NativeLoc byte_value,
                     AggregateAccess);
   void (*bitfield_load)(NativeTarget*, NativeLoc dst_reg,
                         NativeAddr record_addr, BitFieldAccess);
   void (*bitfield_store)(NativeTarget*, NativeAddr record_addr,
                          NativeLoc src_reg, BitFieldAccess);
   void (*binop)(NativeTarget*, BinOp, NativeLoc dst_reg, NativeLoc a_reg,
                 NativeLoc b_reg_or_imm);
   void (*unop)(NativeTarget*, UnOp, NativeLoc dst_reg, NativeLoc src_reg);
   void (*cmp)(NativeTarget*, CmpOp, NativeLoc dst_reg, NativeLoc a_reg,
               NativeLoc b_reg_or_imm);
   void (*convert)(NativeTarget*, ConvKind, NativeLoc dst_reg,
                   NativeLoc src_reg);
   void (*alloca_)(NativeTarget*, NativeLoc dst_reg, NativeLoc size_reg,
                   u32 align);
 
   void (*spill)(NativeTarget*, NativeLoc src_reg, NativeFrameSlot, MemAccess);
   void (*reload)(NativeTarget*, NativeLoc dst_reg, NativeFrameSlot, MemAccess);
 
   void (*plan_call)(NativeTarget*, const NativeCallDesc*, NativeCallPlan*);
   void (*emit_call)(NativeTarget*, const NativeCallPlan*);
   /* `value` is the single returned local's location, or NULL for a void
    * return. out_rets/out_nrets describe the ABI parts of that one value. */
   void (*plan_ret)(NativeTarget*, const CGFuncDesc*, const NativeLoc* value,
                    NativeCallPlanRet** out_rets, u32* out_nrets);
   void (*ret)(NativeTarget*);
 
   void (*atomic_load)(NativeTarget*, NativeLoc dst, NativeAddr addr, MemAccess,
                       KitCgMemOrder);
   void (*atomic_store)(NativeTarget*, NativeAddr addr, NativeLoc src, MemAccess,
                        KitCgMemOrder);
   void (*atomic_rmw)(NativeTarget*, KitCgAtomicOp, NativeLoc dst,
                      NativeAddr addr, NativeLoc val, MemAccess, KitCgMemOrder);
   void (*atomic_cas)(NativeTarget*, NativeLoc prior, NativeLoc ok,
                      NativeAddr addr, NativeLoc expected, NativeLoc desired,
                      MemAccess, KitCgMemOrder success, KitCgMemOrder failure);
   void (*fence)(NativeTarget*, KitCgMemOrder);
   /* Variadic support. The optimizer passes the va_list pointer opaquely as a
    * NativeLoc (a register or memory location holding the address of the
    * va_list object); va_arg additionally receives the argument type and a
    * destination location for the fetched value. All va_list layout knowledge
    * (pointer ABI vs register-save-area ABI, field offsets, sizes) lives behind
    * these hooks, which query the target ABI -- the optimizer makes no layout
    * assumptions. */
   void (*va_start_)(NativeTarget*, NativeLoc ap_ptr);
   void (*va_arg_)(NativeTarget*, NativeLoc dst, NativeLoc ap_ptr,
                   KitCgTypeId type);
   void (*va_end_)(NativeTarget*, NativeLoc ap_ptr);
   void (*va_copy_)(NativeTarget*, NativeLoc dst_ap_ptr, NativeLoc src_ap_ptr);
   void (*intrinsic)(NativeTarget*, IntrinKind, const NativeLoc* dsts, u32 ndst,
                     const NativeLoc* args, u32 narg);
   void (*asm_block)(NativeTarget*, const char* tmpl, const AsmConstraint* outs,
                     u32 nout, NativeLoc* out_locs, const AsmConstraint* ins,
                     u32 nin, const NativeLoc* in_locs, const Sym* clobbers,
                     u32 nclob);
   void (*file_scope_asm)(NativeTarget*, const char* src, size_t len);
   void (*patch_add)(NativeTarget*, const NativePatch*);
   void (*patch_apply)(NativeTarget*);
   void (*trap)(NativeTarget*);
   void (*set_loc)(NativeTarget*, SrcLoc);
   void (*finalize)(NativeTarget*);
   void (*destroy)(NativeTarget*);
 };
 
 static inline const NativeAllocClassInfo*
 native_target_class_info(const NativeTarget* t, NativeAllocClass cls) {
   if (!t || !t->regs) return NULL;
   for (u32 i = 0; i < t->regs->nclasses; ++i) {
     const NativeAllocClassInfo* ci = &t->regs->classes[i];
     if ((NativeAllocClass)ci->cls == cls) return ci;
   }
   return NULL;
 }
 
 static inline u32 native_target_caller_saved_mask(NativeTarget* t,
                                                   NativeAllocClass cls) {
   const NativeAllocClassInfo* ci;
   if (t && t->caller_saved_mask) return t->caller_saved_mask(t, cls);
   ci = native_target_class_info(t, cls);
   return ci ? ci->caller_saved_mask : 0u;
 }
 
 static inline u32 native_target_callee_saved_mask(NativeTarget* t,
                                                   NativeAllocClass cls) {
   const NativeAllocClassInfo* ci;
   if (t && t->callee_saved_mask) return t->callee_saved_mask(t, cls);
   ci = native_target_class_info(t, cls);
   return ci ? ci->callee_saved_mask : 0u;
 }
 
 static inline NativeLoc native_loc_none(void) {
   NativeLoc loc;
   memset(&loc, 0, sizeof loc);
   loc.kind = NATIVE_LOC_NONE;
   return loc;
 }
 
 /* Target-neutral location constructors and scalar queries. These are
  * byte-identical across the native backends, so they live here as the single
  * source of truth. (loc_reg's register mask differs per arch and stays
  * per-backend.) */
 static inline NativeLoc native_loc_reg(KitCgTypeId type, NativeAllocClass cls,
                                        Reg reg) {
   NativeLoc loc;
   memset(&loc, 0, sizeof loc);
   loc.kind = NATIVE_LOC_REG;
   loc.cls = (u8)cls;
   loc.type = type;
   loc.v.reg = reg;
   return loc;
 }
 
 static inline NativeLoc native_loc_stack(KitCgTypeId type, NativeFrameSlot slot,
                                          i32 offset) {
   NativeLoc loc;
   memset(&loc, 0, sizeof loc);
   loc.kind = NATIVE_LOC_STACK;
   loc.cls = NATIVE_REG_INT;
   loc.type = type;
   loc.v.stack.slot = slot;
   loc.v.stack.offset = offset;
   return loc;
 }
 
 static inline int native_loc_is_fp(NativeLoc loc) {
   return (NativeAllocClass)loc.cls == NATIVE_REG_FP;
 }
 
 /* Scalar size/align, clamped to a usable register-sized default. Shared by the
  * backends whose scalars are at most pointer-width (x64, rv64); aa64 keeps its
  * own size query because it asserts on over-wide scalars. */
 static inline u32 native_type_size(NativeTarget* t, KitCgTypeId type) {
   u64 n = type ? cg_type_size(t->c, type) : 8u;
   if (n == 0) n = 8u;
   return (u32)n;
 }
 
 static inline u32 native_type_align(NativeTarget* t, KitCgTypeId type) {
   u64 n = type ? cg_type_align(t->c, type) : 8u;
   if (n == 0) n = 1u;
   if (n > 16u) n = 16u;
   return (u32)n;
 }
 
 static inline MemAccess native_mem_for_type(NativeTarget* t, KitCgTypeId type,
                                             u32 size) {
   MemAccess m;
   memset(&m, 0, sizeof m);
   m.type = type;
   m.size = size ? size : native_type_size(t, type);
   m.align = native_type_align(t, type);
   return m;
 }
 
 /* FP register class for a scalar type: a float value lives in an FP register
  * only when the hardware float ABI has a register that wide. flen comes from
  * the target float ABI (SINGLE->4, DOUBLE->8, SOFT->0); the DEFAULT/unset
  * sentinel maps to the pointer width, which preserves the historical "FP iff
  * float and <= 8 bytes" behavior for lp64d / x86-64 and yields the correct
  * rv32 soft-double result (double is 8 bytes > flen=4 on ilp32f, > 0 on ilp32,
  * so it is INT-class and never bit-cast through an FP register via fmv.d.x).
  * aa64 keeps its own (same predicate, distinct mem helper). */
 static inline NativeAllocClass native_class_for_type_fp_le8(NativeTarget* t,
                                                             KitCgTypeId type) {
   u32 flen;
   switch (t->c->target.float_abi) {
     case KIT_FLOAT_ABI_SINGLE: flen = 4u; break;
     case KIT_FLOAT_ABI_DOUBLE: flen = 8u; break;
     case KIT_FLOAT_ABI_SOFT: flen = 0u; break;
     default: flen = t->c->target.ptr_size; break; /* DEFAULT: historical */
   }
   if (type && flen && cg_type_is_float(t->c, type) &&
       cg_type_size(t->c, type) <= flen)
     return NATIVE_REG_FP;
   return NATIVE_REG_INT;
 }
 
 #endif