kit

abi_rv64.c (12718B)

---

 /* RISC-V ABI dispatch (shared LP64* / ILP32* classifier).
  *
  * One descriptor-parameterized classifier serves both XLENs. The descriptor is
  * derived per call from a->c->target:
  *   gpr_bytes           = target.ptr_size (4 on rv32, 8 on rv64)
  *   aggregate_gpr_bytes = 2 * gpr_bytes (8 on rv32, 16 on rv64)
  *   flen                = FP register width in bytes from target.float_abi:
  *                           DOUBLE -> 8, SINGLE -> 4, SOFT -> 0,
  *                           DEFAULT(unset) -> gpr_bytes (preserves the old
  *                           rv64 LP64D behavior byte-for-byte).
  *
  * Covers the subset the cg test harness exercises plus the RISC-V psABI
  * floating-point aggregate refinements:
  *   void          -> IGNORE
  *   integer ≤ XLEN -> DIRECT, one INT part (a0..a7 for args; a0 for return)
  *   pointer       -> DIRECT, one INT part
  *   float/double  -> DIRECT, one FP part when FP-eligible (fa0..fa7 for args;
  *                    fa0 for return); otherwise INT (and a 2*XLEN scalar
  *                    becomes a GPR pair).
  *   small struct  -> DIRECT:
  *                    * homogeneous FP aggregate (1 or 2 same-kind FP fields,
  *                      ignoring empty/zero-size fields and zero-length arrays)
  *                      -> FP parts (fa pair) when FP-eligible;
  *                    * one FP + one INT scalar (in either order, ≤ 2*XLEN)
  *                      -> (fa, a) or (a, fa) pair;
  *                    * otherwise INT parts up to 2*XLEN (passed in up to 2
  * GPRs). large struct  -> INDIRECT (sret for return; byval for args)
  *
  * Long double is IEEE-754 binary128 (quad) and __int128 are 16-byte scalars
  * passed/returned in an aligned pair of integer registers (low-order half in
  * the lower-numbered register). On rv64 this is the size==2*gpr_bytes pair
  * path; there are no 128-bit FP registers. On rv32 a 64-bit scalar (i64, or a
  * soft-float double) is the size==2*gpr_bytes even-GPR pair.
  *
  * Variadic args bypass these rules entirely and always go through the
  * integer register file / stack (handled at the caller / callee sites). */
 
 #include <string.h>
 
 #include "abi/abi_internal.h"
 #include "cg/type.h"
 #include "core/arena.h"
 #include "core/core.h"
 
 /* Per-call ABI descriptor derived from the target spec. */
 typedef struct RiscvAbiDesc {
   u32 gpr_bytes;           /* XLEN in bytes: 4 (rv32) or 8 (rv64) */
   u32 aggregate_gpr_bytes; /* 2 * gpr_bytes: the small-struct register cap */
   u32 flen;                /* FP register width in bytes: 0, 4, or 8 */
 } RiscvAbiDesc;
 
 static RiscvAbiDesc riscv_abi_desc(TargetABI* a) {
   RiscvAbiDesc d;
   d.gpr_bytes = a->c->target.ptr_size ? a->c->target.ptr_size : 8u;
   d.aggregate_gpr_bytes = 2u * d.gpr_bytes;
   switch (a->c->target.float_abi) {
     case KIT_FLOAT_ABI_DOUBLE:
       d.flen = 8u;
       break;
     case KIT_FLOAT_ABI_SINGLE:
       d.flen = 4u;
       break;
     case KIT_FLOAT_ABI_SOFT:
       d.flen = 0u;
       break;
     case KIT_FLOAT_ABI_DEFAULT:
     default:
       /* Unset: preserve the historical rv64 LP64D behavior, i.e. treat the FP
        * register width as the GPR width (flen == 8 on rv64). */
       d.flen = d.gpr_bytes;
       break;
   }
   return d;
 }
 
 /* An FP scalar of `size` bytes can be carried in an FP register iff the float
  * ABI is hard and the value fits: float (4) needs flen>=4; double (8) needs
  * flen>=8. With soft float (flen==0) nothing is FP-eligible. */
 static int riscv_fp_eligible(u32 flen, u32 size) {
   return flen != 0u && size <= flen;
 }
 
 /* Walk a record collecting the leaf scalars in ABI order, skipping
  * zero-size members (empty structs, zero-length arrays, zero-width
  * bitfields). Returns the number of leaves collected, or > cap if the
  * record has too many leaves to inspect (caller falls back to GPR pair). */
 typedef struct AbiLeaf {
   u32 offset;     /* byte offset within the outermost aggregate */
   u32 size;       /* leaf scalar size in bytes */
   u8 scalar_kind; /* ABIScalarKind */
 } AbiLeaf;
 
 static u32 riscv_collect_leaves(TargetABI* a, KitCgTypeId tid, u32 base_off,
                                 AbiLeaf* out, u32 cap, u32 written) {
   const CgType* t = cg_type_get(a->c, tid);
   if (!t) return written + 1u; /* poison: treat as too-many */
   if (t->kind == KIT_CG_TYPE_RECORD) {
     if (t->record.is_union) return cap + 1u; /* unions: bail */
     for (u32 i = 0; i < t->record.nfields; ++i) {
       const CgTypeField* f = &t->record.fields[i];
       /* Skip bitfields explicitly: a bitfield with bit_width 0 is a layout
        * barrier, a non-zero bitfield kills FP-aggregate classification per
        * the psABI (treat the whole record as GPR-pair). */
       if (f->bit_width != 0) return cap + 1u;
       u32 off = base_off + (u32)f->offset;
       written = riscv_collect_leaves(a, f->type, off, out, cap, written);
       if (written > cap) return written;
     }
     return written;
   }
   if (t->kind == KIT_CG_TYPE_ARRAY) {
     if (t->array.count == 0) return written; /* zero-length array: skip */
     ABITypeInfo elem = abi_cg_type_info(a, t->array.elem);
     if (elem.size == 0) return written;
     for (u64 i = 0; i < t->array.count; ++i) {
       u32 off = base_off + (u32)(i * elem.size);
       written = riscv_collect_leaves(a, t->array.elem, off, out, cap, written);
       if (written > cap) return written;
     }
     return written;
   }
   /* Scalar leaf (including pointer). */
   ABITypeInfo ti = abi_cg_type_info(a, tid);
   if (ti.size == 0) return written;
   if (written >= cap) return written + 1u;
   out[written].offset = base_off;
   out[written].size = ti.size;
   out[written].scalar_kind = ti.scalar_kind;
   return written + 1u;
 }
 
 static void classify_scalar(TargetABI* a, KitCgTypeId t, ABIArgInfo* out) {
   RiscvAbiDesc d = riscv_abi_desc(a);
   ABITypeInfo ti = abi_cg_type_info(a, t);
   /* A scalar twice the GPR width that lives in the integer/long-double space
    * (or a soft-float double) is carried as an aligned pair of GPRs. On rv64
    * this is the 16-byte long double / __int128 pair; on rv32 it is the 8-byte
    * i64 / soft-double pair. A double is only excluded from the pair here when
    * it is FP-eligible (handled by the single-FP-part path below). */
   int fp_part =
       (ti.scalar_kind == ABI_SC_FLOAT) && riscv_fp_eligible(d.flen, ti.size);
   if (ti.size == 2u * d.gpr_bytes && !fp_part &&
       (ti.scalar_kind == ABI_SC_INT || ti.scalar_kind == ABI_SC_FLOAT)) {
     ABIArgPart* parts = arena_array(a->c->tu, ABIArgPart, 2);
     memset(parts, 0, sizeof(ABIArgPart) * 2);
     parts[0].cls = ABI_CLASS_INT;
     parts[0].loc = ABI_LOC_REG;
     parts[0].size = d.gpr_bytes;
     parts[0].align = d.gpr_bytes;
     parts[0].src_offset = 0;
     parts[1].cls = ABI_CLASS_INT;
     parts[1].loc = ABI_LOC_REG;
     parts[1].size = d.gpr_bytes;
     parts[1].align = d.gpr_bytes;
     parts[1].src_offset = d.gpr_bytes;
     out->kind = ABI_ARG_DIRECT;
     out->flags = ABI_AF_NONE;
     out->parts = parts;
     out->nparts = 2;
     out->indirect_align = 0;
     return;
   }
   abi_classify_scalar_reg_part(a, out, ti, fp_part);
 }
 
 static u32 riscv32_scalar_split_lane_size(TargetABI* a, KitCgTypeId t) {
   RiscvAbiDesc d = riscv_abi_desc(a);
   ABITypeInfo ti = abi_cg_type_info(a, t);
   int fp_part;
   if (d.gpr_bytes != 4u) return 0;
   fp_part =
       (ti.scalar_kind == ABI_SC_FLOAT) && riscv_fp_eligible(d.flen, ti.size);
   if (ti.size == 2u * d.gpr_bytes && !fp_part &&
       (ti.scalar_kind == ABI_SC_INT || ti.scalar_kind == ABI_SC_FLOAT))
     return d.gpr_bytes;
   return 0;
 }
 
 /* Try the psABI floating-point aggregate refinements. Returns 1 if `out`
  * was populated, 0 to fall back to the generic GPR-pair packing. */
 static int riscv_classify_fp_aggregate(TargetABI* a, KitCgTypeId t,
                                        const RiscvAbiDesc* d, ABIArgInfo* out) {
   AbiLeaf leaves[2];
   u32 n = riscv_collect_leaves(a, t, 0, leaves, /*cap=*/2u, /*written=*/0u);
   /* n > 2: bail; n == 0: caller already handled zero-size aggregates. */
   if (n == 0 || n > 2) return 0;
 
   u32 nfp = 0;
   for (u32 i = 0; i < n; ++i) {
     if (leaves[i].scalar_kind == ABI_SC_FLOAT) {
       /* An FP leaf only stays in the FP file when it is FP-eligible. With
        * soft float, or a double wider than flen, the aggregate must fall
        * back to the GPR-pair path. */
       if (!riscv_fp_eligible(d->flen, leaves[i].size)) return 0;
       ++nfp;
     }
     /* ABI_SC_INT, ABI_SC_BOOL, ABI_SC_PTR all go to the GPR side. */
   }
   if (nfp == 0) return 0; /* pure-INT goes through the GPR-pair path. */
 
   /* Build the part list in source order so that downstream codegen can
    * align src_offset with the record's field layout. */
   ABIArgPart* parts = arena_array(a->c->tu, ABIArgPart, n);
   memset(parts, 0, sizeof(ABIArgPart) * n);
   for (u32 i = 0; i < n; ++i) {
     parts[i].loc = ABI_LOC_REG;
     parts[i].size = leaves[i].size;
     parts[i].align = leaves[i].size ? leaves[i].size : 1u;
     parts[i].src_offset = leaves[i].offset;
     parts[i].cls =
         (leaves[i].scalar_kind == ABI_SC_FLOAT) ? ABI_CLASS_FP : ABI_CLASS_INT;
   }
   out->kind = ABI_ARG_DIRECT;
   out->flags = ABI_AF_NONE;
   out->parts = parts;
   out->nparts = n;
   out->indirect_align = 0;
   return 1;
 }
 
 static void classify_aggregate(TargetABI* a, KitCgTypeId t, ABIArgInfo* out,
                                int is_return) {
   RiscvAbiDesc d = riscv_abi_desc(a);
   ABITypeInfo ti = abi_cg_type_info(a, t);
   if (ti.size == 0) {
     abi_classify_void(out);
     return;
   }
   if (ti.size <= d.aggregate_gpr_bytes) {
     /* Per psABI: try the FP-aware refinement first (HFA / fp+int pair). */
     if (riscv_classify_fp_aggregate(a, t, &d, out)) return;
     u32 nparts = (ti.size + d.gpr_bytes - 1u) / d.gpr_bytes;
     ABIArgPart* parts = arena_array(a->c->tu, ABIArgPart, nparts);
     memset(parts, 0, sizeof(ABIArgPart) * nparts);
     u32 off = 0;
     for (u32 i = 0; i < nparts; ++i) {
       u32 chunk = (ti.size - off > d.gpr_bytes) ? d.gpr_bytes : (ti.size - off);
       parts[i].cls = ABI_CLASS_INT;
       parts[i].loc = ABI_LOC_REG;
       parts[i].size = chunk;
       parts[i].align = d.gpr_bytes;
       parts[i].src_offset = off;
       off += chunk;
     }
     out->kind = ABI_ARG_DIRECT;
     out->flags = ABI_AF_NONE;
     out->parts = parts;
     out->nparts = nparts;
     out->indirect_align = 0;
   } else {
     out->kind = ABI_ARG_INDIRECT;
     out->flags = is_return ? ABI_AF_SRET : ABI_AF_BYVAL;
     out->indirect_align = ti.align ? ti.align : d.gpr_bytes;
     out->parts = NULL;
     out->nparts = 0;
   }
   (void)is_return;
 }
 
 static void classify_one(TargetABI* a, KitCgTypeId t, ABIArgInfo* out,
                          int is_return) {
   const CgType* ty = cg_type_get(a->c, t);
   if (!ty || ty->kind == KIT_CG_TYPE_VOID) {
     abi_classify_void(out);
     return;
   }
   switch (ty->kind) {
     case KIT_CG_TYPE_RECORD:
       classify_aggregate(a, t, out, is_return);
       return;
     default:
       classify_scalar(a, t, out);
       return;
   }
 }
 
 static ABIFuncInfo* riscv_compute_func_info(TargetABI* a, KitCgTypeId fn) {
   /* RISC-V passes the sret pointer in a0 (the first integer arg register),
    * consuming that slot, so sret_consumes_int_arg follows has_sret. */
   return abi_compute_func_info_generic(a, fn, classify_one,
                                        /*sret_consumes_int_arg=*/1);
 }
 
 const ABIVtable rv64_vtable = {
     .compute_func_info = riscv_compute_func_info,
     .va_list_info = {8, 8, ABI_SC_PTR, 0, 0, 0},
     /* LP64D va_list is a plain pointer, but the variadic register-save area is
      * the 8 integer arg registers (a0..a7) spilled contiguously = 64 bytes; FP
      * varargs are passed in GPRs, so there is no separate FP save area. The
      * gp_reg_count/gp_slot_size fields let native_frame_va_save_bytes size that
      * area from the ABI rather than a backend constant. */
     .va_list_layout = {.kind = ABI_VA_LIST_POINTER,
                        .gp_reg_count = 8,
                        .fp_reg_count = 0,
                        .gp_slot_size = 8,
                        .fp_slot_size = 0},
 };
 
 const ABIVtable rv32_vtable = {
     .compute_func_info = riscv_compute_func_info,
     .scalar_split_lane_size = riscv32_scalar_split_lane_size,
     .va_list_info = {4, 4, ABI_SC_PTR, 0, 0, 0},
     /* ILP32* va_list is a plain 4-byte pointer; the variadic register-save
      * area is the 8 integer arg registers (a0..a7) spilled contiguously =
      * 32 bytes. FP varargs are passed in GPRs, so there is no FP save area. */
     .va_list_layout = {.kind = ABI_VA_LIST_POINTER,
                        .gp_reg_count = 8,
                        .fp_reg_count = 0,
                        .gp_slot_size = 4,
                        .fp_slot_size = 0},
 };