riscv64-cvt-int-zext.after (1192B)
1 if ((sbt & VT_BTYPE) != VT_LLONG && 2 (sbt & VT_BTYPE) != VT_PTR && 3 (sbt & VT_BTYPE) != VT_FUNC) { 4 /* need to convert from 32bit to 64bit */ 5 gv(RC_INT); 6 #if defined(TCC_TARGET_RISCV64) 7 /* riscv64: gen_cvt_sxtw handles both directions 8 * (sign- or zero-extend) based on vtop->type. Don't 9 * skip the unsigned case — RV64 32-bit ops sign-extend 10 * their results, so an `unsigned int` register value 11 * may have garbage upper bits that must be cleared 12 * before widening. See riscv64-gen.c. */ 13 gen_cvt_sxtw(); 14 #else 15 if (sbt != (VT_INT | VT_UNSIGNED)) { 16 #if defined(TCC_TARGET_ARM64) 17 gen_cvt_sxtw(); 18 #elif defined(TCC_TARGET_X86_64) 19 int r = gv(RC_INT); 20 /* x86_64 specific: movslq */ 21 o(0x6348); 22 o(0xc0 + (REG_VALUE(r) << 3) + REG_VALUE(r)); 23 #else 24 #error 25 #endif 26 } 27 #endif 28 }