boot2

Playing with the boostrap
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arm64-tok.h (5426B)


      1 /* ARM64 assembler tokens
      2  *
      3  * Order matters for the contiguous-range checks in arm64-asm.c
      4  * (TOK_ASM_x0..xzr, TOK_ASM_w0..wzr, TOK_ASM_eq..nv, TOK_ASM_b_eq..b_nv).
      5  * Aliases (lr/fp/ip0/ip1/wsp) and shift/extend keywords are matched
      6  * by exact token, not by range.
      7  */
      8 
      9 /* X (64-bit) integer registers. Must be contiguous, x0 first. */
     10  DEF_ASM(x0)
     11  DEF_ASM(x1)
     12  DEF_ASM(x2)
     13  DEF_ASM(x3)
     14  DEF_ASM(x4)
     15  DEF_ASM(x5)
     16  DEF_ASM(x6)
     17  DEF_ASM(x7)
     18  DEF_ASM(x8)
     19  DEF_ASM(x9)
     20  DEF_ASM(x10)
     21  DEF_ASM(x11)
     22  DEF_ASM(x12)
     23  DEF_ASM(x13)
     24  DEF_ASM(x14)
     25  DEF_ASM(x15)
     26  DEF_ASM(x16)
     27  DEF_ASM(x17)
     28  DEF_ASM(x18)
     29  DEF_ASM(x19)
     30  DEF_ASM(x20)
     31  DEF_ASM(x21)
     32  DEF_ASM(x22)
     33  DEF_ASM(x23)
     34  DEF_ASM(x24)
     35  DEF_ASM(x25)
     36  DEF_ASM(x26)
     37  DEF_ASM(x27)
     38  DEF_ASM(x28)
     39  DEF_ASM(x29)
     40  DEF_ASM(x30)
     41  DEF_ASM(sp)    /* X-form stack pointer / zero-reg-31 alias */
     42  DEF_ASM(xzr)
     43 
     44 /* W (32-bit) integer registers. Must be contiguous, w0 first. */
     45  DEF_ASM(w0)
     46  DEF_ASM(w1)
     47  DEF_ASM(w2)
     48  DEF_ASM(w3)
     49  DEF_ASM(w4)
     50  DEF_ASM(w5)
     51  DEF_ASM(w6)
     52  DEF_ASM(w7)
     53  DEF_ASM(w8)
     54  DEF_ASM(w9)
     55  DEF_ASM(w10)
     56  DEF_ASM(w11)
     57  DEF_ASM(w12)
     58  DEF_ASM(w13)
     59  DEF_ASM(w14)
     60  DEF_ASM(w15)
     61  DEF_ASM(w16)
     62  DEF_ASM(w17)
     63  DEF_ASM(w18)
     64  DEF_ASM(w19)
     65  DEF_ASM(w20)
     66  DEF_ASM(w21)
     67  DEF_ASM(w22)
     68  DEF_ASM(w23)
     69  DEF_ASM(w24)
     70  DEF_ASM(w25)
     71  DEF_ASM(w26)
     72  DEF_ASM(w27)
     73  DEF_ASM(w28)
     74  DEF_ASM(w29)
     75  DEF_ASM(w30)
     76  DEF_ASM(wsp)
     77  DEF_ASM(wzr)
     78 
     79 /* Register aliases. */
     80  DEF_ASM(lr)     /* x30 */
     81  DEF_ASM(fp)     /* x29 */
     82  DEF_ASM(ip0)    /* x16 */
     83  DEF_ASM(ip1)    /* x17 */
     84 
     85 /* Condition codes. Order must match the 4-bit cond field
     86  * (eq=0..nv=15) for the contiguous-range check in arm64-asm.c. */
     87  DEF_ASM(eq)
     88  DEF_ASM(ne)
     89  DEF_ASM(cs)
     90  DEF_ASM(cc)
     91  DEF_ASM(mi)
     92  DEF_ASM(pl)
     93  DEF_ASM(vs)
     94  DEF_ASM(vc)
     95  DEF_ASM(hi)
     96  DEF_ASM(ls)
     97  DEF_ASM(ge)
     98  DEF_ASM(lt)
     99  DEF_ASM(gt)
    100  DEF_ASM(le)
    101  DEF_ASM(al)
    102  DEF_ASM(nv)
    103 /* Aliases for cond codes — matched by exact token, mapped to numeric values. */
    104  DEF_ASM(hs)     /* alias of cs (=2) */
    105  DEF_ASM(lo)     /* alias of cc (=3) */
    106 
    107 /* Shift specifiers. Used in operand position after a comma. */
    108  DEF_ASM(lsl)
    109  DEF_ASM(lsr)
    110  DEF_ASM(asr)
    111  DEF_ASM(ror)
    112 
    113 /* Extend specifiers. Used in operand position after a comma. */
    114  DEF_ASM(uxtb)
    115  DEF_ASM(uxth)
    116  DEF_ASM(uxtw)
    117  DEF_ASM(uxtx)
    118  DEF_ASM(sxtb)
    119  DEF_ASM(sxth)
    120  DEF_ASM(sxtw)
    121  DEF_ASM(sxtx)
    122 
    123 /* Helper for "b.cond"-style mnemonics: produce a token whose name
    124  * is the C identifier ## but whose source text is "b.<cond>".  */
    125 #define DEF_ASM_DOT(x, y) DEF(TOK_ASM_ ## x ## _ ## y, #x "." #y)
    126 
    127 /* Conditional branches — one token per cond. Order must match
    128  * the cond numeric (eq=0..nv=15) so b_<cond> - b_eq == cond. */
    129  DEF_ASM_DOT(b, eq)
    130  DEF_ASM_DOT(b, ne)
    131  DEF_ASM_DOT(b, cs)
    132  DEF_ASM_DOT(b, cc)
    133  DEF_ASM_DOT(b, mi)
    134  DEF_ASM_DOT(b, pl)
    135  DEF_ASM_DOT(b, vs)
    136  DEF_ASM_DOT(b, vc)
    137  DEF_ASM_DOT(b, hi)
    138  DEF_ASM_DOT(b, ls)
    139  DEF_ASM_DOT(b, ge)
    140  DEF_ASM_DOT(b, lt)
    141  DEF_ASM_DOT(b, gt)
    142  DEF_ASM_DOT(b, le)
    143  DEF_ASM_DOT(b, al)
    144  DEF_ASM_DOT(b, nv)
    145 /* Aliases (b.hs = b.cs, b.lo = b.cc).  */
    146  DEF_ASM_DOT(b, hs)
    147  DEF_ASM_DOT(b, lo)
    148 
    149 /* Mnemonics */
    150  DEF_ASM(mov)
    151  DEF_ASM(add)
    152  DEF_ASM(sub)
    153  DEF_ASM(ldr)
    154  DEF_ASM(str)
    155  DEF_ASM(ldp)
    156  DEF_ASM(stp)
    157  DEF_ASM(b)
    158  DEF_ASM(bl)
    159  DEF_ASM(ret)
    160  DEF_ASM(svc)
    161 
    162 /* DP-immediate. */
    163  DEF_ASM(adds)
    164  DEF_ASM(subs)
    165  DEF_ASM(cmp)
    166  DEF_ASM(cmn)
    167  DEF_ASM(neg)
    168  DEF_ASM(negs)
    169  DEF_ASM(and)
    170  DEF_ASM(orr)
    171  DEF_ASM(eor)
    172  DEF_ASM(ands)
    173  DEF_ASM(tst)
    174  DEF_ASM(movz)
    175  DEF_ASM(movn)
    176  DEF_ASM(movk)
    177  DEF_ASM(sbfm)
    178  DEF_ASM(ubfm)
    179  DEF_ASM(bfm)
    180  DEF_ASM(sbfiz)
    181  DEF_ASM(sbfx)
    182  DEF_ASM(ubfiz)
    183  DEF_ASM(ubfx)
    184  DEF_ASM(bfi)
    185  DEF_ASM(bfxil)
    186 /* lsl/lsr/asr/ror tokens are declared once above as shift specifiers;
    187    they double-duty as mnemonics for the bitfield aliases. Same for
    188    sxtb/sxth/sxtw/uxtb/uxth — single token, dual context. */
    189 
    190 /* DP-register. */
    191  DEF_ASM(bic)
    192  DEF_ASM(orn)
    193  DEF_ASM(eon)
    194  DEF_ASM(bics)
    195  DEF_ASM(mvn)
    196  DEF_ASM(lslv)
    197  DEF_ASM(lsrv)
    198  DEF_ASM(asrv)
    199  DEF_ASM(rorv)
    200  DEF_ASM(mul)
    201  DEF_ASM(mneg)
    202  DEF_ASM(madd)
    203  DEF_ASM(msub)
    204  DEF_ASM(smull)
    205  DEF_ASM(umull)
    206  DEF_ASM(smnegl)
    207  DEF_ASM(umnegl)
    208  DEF_ASM(smaddl)
    209  DEF_ASM(umaddl)
    210  DEF_ASM(smsubl)
    211  DEF_ASM(umsubl)
    212  DEF_ASM(smulh)
    213  DEF_ASM(umulh)
    214  DEF_ASM(udiv)
    215  DEF_ASM(sdiv)
    216  DEF_ASM(csel)
    217  DEF_ASM(csinc)
    218  DEF_ASM(csinv)
    219  DEF_ASM(csneg)
    220  DEF_ASM(cset)
    221  DEF_ASM(csetm)
    222  DEF_ASM(cinc)
    223  DEF_ASM(cinv)
    224  DEF_ASM(cneg)
    225 
    226 /* load/store extras. */
    227  DEF_ASM(ldrb)
    228  DEF_ASM(ldrh)
    229  DEF_ASM(ldrsb)
    230  DEF_ASM(ldrsh)
    231  DEF_ASM(ldrsw)
    232  DEF_ASM(strb)
    233  DEF_ASM(strh)
    234  DEF_ASM(ldur)
    235  DEF_ASM(stur)
    236 
    237 /* branches & system. */
    238  DEF_ASM(cbz)
    239  DEF_ASM(cbnz)
    240  DEF_ASM(tbz)
    241  DEF_ASM(tbnz)
    242  DEF_ASM(br)
    243  DEF_ASM(blr)
    244  DEF_ASM(brk)
    245  DEF_ASM(hlt)
    246  DEF_ASM(hvc)
    247  DEF_ASM(smc)
    248  DEF_ASM(nop)
    249  DEF_ASM(yield)
    250  DEF_ASM(wfe)
    251  DEF_ASM(wfi)
    252  DEF_ASM(sev)
    253  DEF_ASM(sevl)
    254  DEF_ASM(hint)
    255  DEF_ASM(isb)
    256  DEF_ASM(dsb)
    257  DEF_ASM(dmb)
    258 
    259 /* MRS / MSR (system register access) and MSR-immediate (PSTATE field). */
    260  DEF_ASM(mrs)
    261  DEF_ASM(msr)
    262  DEF_ASM(eret)
    263 /* PSTATE field names accepted as the first operand of MSR-immediate.
    264  * Lowercased here; arm64-asm.c does a case-insensitive name lookup
    265  * against the lexed identifier so DAIFSet/DAIFClr also match. */
    266  DEF_ASM(daifset)
    267  DEF_ASM(daifclr)
    268 
    269 /* SYS-instruction aliases (cache / TLB maintenance). */
    270  DEF_ASM(ic)
    271  DEF_ASM(tlbi)
    272 
    273 /* Barrier-scope option names for dsb/dmb. */
    274  DEF_ASM(sy)
    275  DEF_ASM(ish)
    276  DEF_ASM(ishst)
    277  DEF_ASM(ishld)
    278  DEF_ASM(nsh)
    279  DEF_ASM(nshst)
    280  DEF_ASM(nshld)
    281  DEF_ASM(osh)
    282  DEF_ASM(oshst)
    283  DEF_ASM(oshld)